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adi,axi-pwmgen fixes backport #2824

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@dlech dlech commented Jun 18, 2025

PR Description

This is backporting a couple of fixes that were recently upstreamed to correct the clocks binding on adi,axi-pwmgen-2.00.a. Plus a patch to update all of the example .dts files that use it. A couple of .dts files had bugs in the clocks bindings as well, so those are fixed.

I intentionally added one more patch that conflicts with #2823 to remind us that it needs to get merged first so that we can fix up that .dts file as well before merging this one.

PR Type

  • Bug fix (a change that fixes an issue)
  • New feature (a change that adds new functionality)
  • Breaking change (a change that affects other repos or cause CIs to fail)

PR Checklist

  • I have conducted a self-review of my own code changes
  • I have tested the changes on the relevant hardware
  • I have updated the documentation outside this repo accordingly (if there is the case)

dlech added 4 commits June 18, 2025 14:46
Fix a shortcoming in the bindings that doesn't allow for a separate
external clock.

The AXI PWMGEN IP block has a compile option ASYNC_CLK_EN that allows
the use of an external clock for the PWM output separate from the AXI
clock that runs the peripheral.

This was missed in the original bindings and so users were writing dts
files where the one and only clock specified would be the external
clock, if there was one, incorrectly missing the separate AXI clock.

The correct bindings are that the AXI clock is always required and the
external clock is optional (must be given only when HDL compile option
ASYNC_CLK_EN=1).

Fixes: 1edf2c2 ("dt-bindings: pwm: Add AXI PWM generator")
Cc: stable@vger.kernel.org
Signed-off-by: David Lechner <dlechner@baylibre.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250529-pwm-axi-pwmgen-add-external-clock-v3-2-5d8809a7da91@baylibre.com
Signed-off-by: Uwe Kleine-König <ukleinek@kernel.org>
(cherry picked from commit e683131)
Signed-off-by: David Lechner <dlechner@baylibre.com>
Add proper support for external clock to the AXI PWM generator driver.

In most cases, the HDL for this IP block is compiled with the default
ASYNC_CLK_EN=1. With this option, there is a separate external clock
that drives the PWM output separate from the peripheral clock. So the
driver should be enabling the "axi" clock to power the peripheral and
the "ext" clock to drive the PWM output.

When ASYNC_CLK_EN=0, the "axi" clock is also used to drive the PWM
output and there is no "ext" clock.

Previously, if there was a separate external clock, users had to specify
only the external clock and (incorrectly) omit the AXI clock in order
to get the correct operating frequency for the PWM output.

The devicetree bindings are updated to fix this shortcoming and this
patch changes the driver to match the new bindings. To preserve
compatibility with any existing dtbs that specify only one clock, we
don't require the clock name on the first clock.

Fixes: 41814fe ("pwm: Add driver for AXI PWM generator")
Cc: stable@vger.kernel.org
Acked-by: Nuno Sá <nuno.sa@analog.com>
Reviewed-by: Trevor Gamblin <tgamblin@baylibre.com>
Signed-off-by: David Lechner <dlechner@baylibre.com>
Link: https://lore.kernel.org/r/20250529-pwm-axi-pwmgen-add-external-clock-v3-3-5d8809a7da91@baylibre.com
Signed-off-by: Uwe Kleine-König <ukleinek@kernel.org>
(cherry picked from commit a8841dc)
Signed-off-by: David Lechner <dlechner@baylibre.com>
After backporting the dt-bindings fix from upstream, update the existing
.dts files that use adi,axi-pwmgen-2.00.a to use the corrected clocks
binding.

In the HDL, ASYNC_CLK_EN=1 by default, so most projects have a separate
external clock. The only exceptions are ad7606x, ad7616 and dc2677a,
which have ASYNC_CLK_EN=0 and therefore only one clock.

In arch/arm/boot/dts/xilinx/zynq-zed-adv7511-ad4134.dts the wrong clock
was specified for the old binding so it will have a behavior change to
use the correct clock for the PWM clock rate now.

In arch/arm/boot/dts/xilinx/zynq-zed-adv7511-ltc2387.dts, we also drop
the 0 in the phandle since #clock-cells = <0>; for &ref_clk.

Signed-off-by: David Lechner <dlechner@baylibre.com>
This is the same as analogdevicesinc#2823
but has the adi,axi-pwmgen bindings clocks fixed up.

We can drop this and add the fixup to the previous patch after the other
PR is merged.

Signed-off-by: David Lechner <dlechner@baylibre.com>
@@ -72,8 +72,8 @@
reg = <0x44b00000 0x1000>;
label = "ad463x_cnv";
#pwm-cells = <2>;
clocks = <&cnv_ext_clk>;

clocks = <&clkc 15>, <&spi_clk>;
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Suggested change
clocks = <&clkc 15>, <&spi_clk>;
clocks = <&clkc 15>, <&cnv_ext_clk>;

oops

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