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arm: dts: xilinx: add example for ADAQ4380-4 eval board #2823

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arm: dts: xilinx: add example for ADAQ4380-4 eval board #2823

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143 changes: 143 additions & 0 deletions arch/arm/boot/dts/xilinx/zynq-zed-adv7511-adaq4380-4.dts
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// SPDX-License-Identifier: GPL-2.0
/*
* Analog Devices ADAQ4380-4
* https://www.analog.com/media/en/technical-documentation/data-sheets/adaq4380-4.pdf
* https://www.analog.com/media/en/technical-documentation/user-guides/eval-adaq4380-4-4370-4-4381-4-ug-2224.pdf
* https://wiki.analog.com/resources/tools-software/linux-drivers/iio-adc/ad738x
* http://analogdevicesinc.github.io/hdl/projects/ad738x_fmc/index.html
*
* hdl_project: <ad738x_fmc/zed>
* board_revision: <>
*
* Copyright (C) 2025 Analog Devices Inc.
*/
/dts-v1/;

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>

#include "zynq-zed.dtsi"
#include "zynq-zed-adv7511.dtsi"

/ {
eval_u3: eval-board-u3-regulator {
compatible = "regulator-fixed";
regulator-name = "EVAL +5V supply (U3)";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
};

eval_gnd: eval-board-gnd-regulator {
compatible = "regulator-fixed";
regulator-name = "EVAL GND (0V) supply";
regulator-always-on;
};
Comment on lines +31 to +35
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Interesting this one. We would normally assume GND supply pins connected to GND and not declare any GND supply in dt. Though, I see VS- may range from -5V to GND so I think it makes sense to explicitly provide the supply in this case.

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Yes, that was the conclusion from upstream review as well.


// technically, the ADC node should be a regulator provider instead of this
adc_ldo: adc-ldo-regulator {
compatible = "regulator-fixed";
regulator-name = "ADC LDO output";
regulator-always-on;
};

trigger_pwm: adc-pwm-trigger {
compatible = "pwm-trigger";
#trigger-source-cells = <0>;
pwms = <&adc_trigger 0 10000 0>;
};
};

&fpga_axi {
adc_trigger: pwm@44b00000 {
compatible = "adi,axi-pwmgen-2.00.a";
reg = <0x44b00000 0x1000>;
#pwm-cells = <3>;
clocks = <&spi_clk>;
};

spi_clk: clock-controller@44a70000 {
compatible = "adi,axi-clkgen-2.00.a";
reg = <0x44a70000 0x1000>;
#clock-cells = <0>;
clocks = <&clkc 15>, <&clkc 15>;
clock-names = "clkin1", "s_axi_aclk";
clock-output-names = "spi_clk";
assigned-clocks = <&spi_clk>;
assigned-clock-rates = <160000000>;
};

rx_dma: dma-controller@44a30000 {
compatible = "adi,axi-dmac-1.00.a";
reg = <0x44a30000 0x1000>;
#dma-cells = <1>;
interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkc 15>;
};

axi_spi_engine_0: spi@44a00000 {
compatible = "adi,axi-spi-engine-1.00.a";
reg = <0x44a00000 0x1000>;
interrupt-parent = <&intc>;
interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkc 15>, <&spi_clk>;
clock-names = "s_axi_aclk", "spi_clk";

dmas = <&rx_dma 0>;
dma-names = "offload0-rx";
trigger-sources = <&trigger_pwm>;

#address-cells = <1>;
#size-cells = <0>;

adc@0 {
compatible = "adi,adaq4380-4";
reg = <0>;

spi-cpol;
spi-max-frequency = <80000000>;

/*
* ADI tree extension (not mainline). Set this based on
* HDL NUM_OF_SDI compile argument. Can omit if =1.
* REVISIT: replace this upstream equivalent when it
* becomes available.
*/
adi,num-sdi = <4>;
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adi,ad4030.yaml (upstream) documents spi-rx-bus-width and that is also intended to match a NUM_OF_SDI HDL build parameter (on the ad4630_fmc hdl project). On the ad4630_fmc project, the NUM_OF_SDI specifies how many SDO lines are used for each channel. Would it make sense to use the same property name here? If not, might be a good idea to add a comment telling how this is different from adi,ad4030.yaml spi-rx-bus-width (or add a TODO tag to remind this will need to be updated). Currently, ADI Linux adi,ad4630.yaml uses adi,lane-mode to tell what NUM_OF_SDI was the HDL built with, but I guess it's safe to assume that prop will also be updated at some point.

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@dlech dlech Jun 20, 2025 •
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spi-rx-bus-width is not the same as multiple buses. spi-rx-bus-width lets you read multiple bits of the same word at one time. But multiple buses lets you read one bit each of multiple words at the same time. AD4630 has both actually (i.e. 8 SDO lines consisting of 2 buses and 4 bits per bus), but this chip only has multiple buses.

There is a proposed upstream binding for multiple buses currently on the mailing lists right now and I'm working with the HDL engineers to adapt the AXI SPI Engine to do something like that as well so that we can have proper upstream support.


vcc-supply = <&adc_ldo>;
vlogic-supply = <&adc_ldo>;
refin-supply = <&eval_u3>;
vs-p-supply = <&eval_u3>;
vs-n-supply = <&eval_gnd>;
ldo-supply = <&eval_u3>;

#address-cells = <1>;
#size-cells = <0>;

channel@0 {
reg = <0>;
// depends on LKA jumper positions
adi,gain-milli = /bits/ 16 <300>;
};

channel@1 {
reg = <1>;
// depends on LKB jumper positions
adi,gain-milli = /bits/ 16 <300>;
};

channel@2 {
reg = <2>;
// depends on LKC jumper positions
adi,gain-milli = /bits/ 16 <300>;
};

channel@3 {
reg = <3>;
// depends on LKD jumper positions
adi,gain-milli = /bits/ 16 <300>;
};
};
};
};