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Add support for AD4052 ADC Family #2642
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2ac66a2
Add support for AD4052 device family
gastmaier b17bb2b
Documentation: ABI: add events sampling frequency in sysfs-bus-iio
gastmaier 989d385
Documentation: ABI: add oversampling frequency in sysfs-bus-iio
gastmaier 1265b93
iio: code: mark iio_dev as const in iio_buffer_enabled
gastmaier a06505c
dt-bindings: iio: adc: Add adi,ad4052
gastmaier 12165ac
arch: arm: boot: add AD4052 dts for Coraz7s
gastmaier d77c3e4
docs: iio: new docs for ad4052 driver
gastmaier aba6154
iio: adc: add support for ad4052
gastmaier 13df15e
Kconfig.adi: imply AD4052
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) | ||
# Copyright 2025 Analog Devices Inc. | ||
%YAML 1.2 | ||
--- | ||
$id: http://devicetree.org/schemas/iio/adc/adi,ad4052.yaml# | ||
$schema: http://devicetree.org/meta-schemas/core.yaml# | ||
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title: Analog Devices AD4052 ADC family device driver | ||
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maintainers: | ||
- Jorge Marques <jorge.marques@analog.com> | ||
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description: | | ||
Analog Devices AD4052 Single Channel Precision SAR ADC family | ||
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https://www.analog.com/media/en/technical-documentation/data-sheets/ad4050-ad4056.pdf | ||
https://www.analog.com/media/en/technical-documentation/data-sheets/ad4052-ad4058.pdf | ||
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properties: | ||
compatible: | ||
enum: | ||
- adi,ad4050 | ||
- adi,ad4052 | ||
- adi,ad4056 | ||
- adi,ad4058 | ||
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reg: | ||
maxItems: 1 | ||
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interrupts: | ||
items: | ||
- description: Signal coming from the GP0 pin (threshold). | ||
- description: Signal coming from the GP1 pin (data ready). | ||
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interrupt-names: | ||
items: | ||
- const: gp0 | ||
- const: gp1 | ||
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gpio-controller: true | ||
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"#gpio-cells": | ||
const: 2 | ||
description: | | ||
The first cell is the GPn number: 0 to 1. | ||
The second cell takes standard GPIO flags. | ||
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cnv-gpios: | ||
description: The Convert Input (CNV). If omitted, CNV is tied to SPI CS. | ||
maxItems: 1 | ||
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spi-max-frequency: | ||
maximum: 62500000 | ||
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vdd-supply: | ||
description: Analog power supply. | ||
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vio-supply: | ||
description: Digital interface logic power supply. | ||
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vref-supply: | ||
description: Reference voltage to set the ADC full-scale range. | ||
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required: | ||
- compatible | ||
- reg | ||
- vdd-supply | ||
- vio-supply | ||
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allOf: | ||
- $ref: /schemas/spi/spi-peripheral-props.yaml# | ||
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unevaluatedProperties: false | ||
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examples: | ||
- | | ||
#include <dt-bindings/gpio/gpio.h> | ||
#include <dt-bindings/interrupt-controller/irq.h> | ||
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spi { | ||
#address-cells = <1>; | ||
#size-cells = <0>; | ||
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adc@0 { | ||
compatible = "adi,ad4052"; | ||
reg = <0>; | ||
vdd-supply = <&adc_vdd>; | ||
vio-supply = <&adc_vio>; | ||
spi-max-frequency = <25000000>; | ||
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interrupt-parent = <&gpio>; | ||
interrupts = <0 0 IRQ_TYPE_EDGE_RISING>, | ||
<0 1 IRQ_TYPE_EDGE_FALLING>; | ||
interrupt-names = "gp0", "gp1"; | ||
cnv-gpios = <&gpio 2 GPIO_ACTIVE_HIGH>; | ||
}; | ||
}; | ||
... | ||
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.. SPDX-License-Identifier: GPL-2.0-only | ||
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============= | ||
AD4052 driver | ||
============= | ||
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ADC driver for Analog Devices Inc. AD4052 and similar devices. | ||
The module name is ``ad4052``. | ||
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Supported devices | ||
================= | ||
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The following chips are supported by this driver: | ||
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* `AD4050 <https://www.analog.com/AD4050>`_ | ||
* `AD4052 <https://www.analog.com/AD4052>`_ | ||
* `AD4056 <https://www.analog.com/AD4056>`_ | ||
* `AD4058 <https://www.analog.com/AD4058>`_ | ||
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Wiring modes | ||
============ | ||
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The ADC uses SPI 4-wire mode, and contain two programmable GPIOs and | ||
a CNV pin. | ||
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The CNV pin is exposed as the ``cnv-gpios`` and triggers a ADC conversion. | ||
GP1 is ADC conversion ready signal and GP0 Threshold event interrupt, both | ||
exposed as interrupts. | ||
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Omit ``cnv-gpios`` and tie CNV and CS together to use the rising edge | ||
of the CS as the CNV signal. | ||
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Device attributes | ||
================= | ||
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The ADC contain only one channels, and the following attributes: | ||
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.. list-table:: Driver attributes | ||
:header-rows: 1 | ||
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* - Attribute | ||
- Description | ||
* - ``in_voltage0_raw`` | ||
- Raw ADC voltage value | ||
* - ``in_voltage0_oversampling_ratio`` | ||
- Enable the device's burst averaging mode to over sample using | ||
the internal sample rate. | ||
* - ``in_voltage0_oversampling_ratio_available`` | ||
- List of available oversampling values. Value 0 disable the burst | ||
averaging mode. | ||
* - ``conversion_frequency`` | ||
- Device internal sample rate used in the burst averaging mode. | ||
* - ``conversion_frequency_available`` | ||
- List of available sample rates. | ||
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Threshold events | ||
================ | ||
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The ADC supports a monitoring mode to raise threshold events. | ||
The driver supports a single interrupt for both rising and falling | ||
readings. | ||
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The feature is enabled/disabled by setting ``thresh_either_en``. | ||
During monitor mode, the device continuously operates in autonomous mode until | ||
put back in configuration mode, due to this, the device returns busy until the | ||
feature is disabled. | ||
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Low-power mode | ||
============== | ||
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The device enters low-power mode on idle to save power. | ||
Enabling an event puts the device out of the low-power since the ADC | ||
autonomously samples to assert the event condition. | ||
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SPI offload support | ||
=================== | ||
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To be able to achieve the maximum sample rate, the driver can be used with the | ||
`AXI SPI Engine`_ to provide SPI offload support. | ||
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.. _AXI SPI Engine: http://analogdevicesinc.github.io/hdl/projects/ad4052_ardz/index.html | ||
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When SPI offload is being used, additional attributes are present: | ||
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.. list-table:: Additional attributes | ||
:header-rows: 1 | ||
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* - Attribute | ||
- Description | ||
* - ``in_voltage0_sampling_frequency`` | ||
- Set the sampling frequency. | ||
* - ``in_voltage0_sampling_frequency_available`` | ||
- Get the sampling frequency range. | ||
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The scan type is different when the buffer with offload support is enabled. |
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// SPDX-License-Identifier: GPL-2.0 | ||
/* | ||
* Analog Devices AD4052 | ||
* | ||
* hdl_project: <ad4052_ardz/coraz7s> | ||
* | ||
* Copyright (C) 2025 Analog Devices Inc. | ||
*/ | ||
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/dts-v1/; | ||
#include "zynq-coraz7s.dtsi" | ||
#include <dt-bindings/interrupt-controller/irq.h> | ||
#include <dt-bindings/gpio/gpio.h> | ||
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/ { | ||
adc_vdd: regulator-vref-adc { | ||
compatible = "regulator-fixed"; | ||
regulator-name = "adc-vdd"; | ||
regulator-min-microvolt = <3600000>; | ||
regulator-max-microvolt = <3600000>; | ||
regulator-always-on; | ||
}; | ||
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adc_vio: regulator-vio-adc { | ||
compatible = "regulator-fixed"; | ||
regulator-name = "adc_vio"; | ||
regulator-min-microvolt = <3600000>; | ||
regulator-max-microvolt = <3600000>; | ||
regulator-always-on; | ||
}; | ||
}; | ||
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&fpga_axi { | ||
axi_iic: i2c@41600000 { | ||
compatible = "xlnx,axi-iic-1.01.b", "xlnx,xps-iic-2.00.a"; | ||
reg = <0x41600000 0x10000>; | ||
interrupt-parent = <&intc>; | ||
interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>; | ||
clocks = <&clkc 15>; | ||
clock-names = "s_axi_aclk"; | ||
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#size-cells = <0>; | ||
#address-cells = <1>; | ||
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eeprom1: eeprom@52 { | ||
compatible = "atmel,24c32"; | ||
reg = <0x52>; | ||
}; | ||
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}; | ||
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rx_dma: rx-dmac@44a30000 { | ||
compatible = "adi,axi-dmac-1.00.a"; | ||
reg = <0x44a30000 0x1000>; | ||
#dma-cells = <1>; | ||
interrupt-parent = <&intc>; | ||
interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>; | ||
clocks = <&clkc 15>; | ||
}; | ||
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spi_clk: axi-clkgen@44a70000 { | ||
compatible = "adi,axi-clkgen-2.00.a"; | ||
reg = <0x44a70000 0x10000>; | ||
#clock-cells = <0>; | ||
clocks = <&clkc 15>, <&clkc 15>; | ||
clock-names = "s_axi_aclk", "clkin1"; | ||
clock-output-names = "spi_clk"; | ||
}; | ||
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adc_trigger: pwm@44b00000 { | ||
compatible = "adi,axi-pwmgen-2.00.a"; | ||
reg = <0x44b00000 0x1000>; | ||
#pwm-cells = <2>; | ||
clocks = <&spi_clk>; | ||
}; | ||
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axi_spi_engine: spi@44a00000 { | ||
compatible = "adi,axi-spi-engine-1.00.a"; | ||
reg = <0x44a00000 0x1FF>; | ||
interrupt-parent = <&intc>; | ||
interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>; | ||
clocks = <&clkc 15>, <&spi_clk>; | ||
clock-names = "s_axi_aclk", "spi_clk"; | ||
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dmas = <&rx_dma 0>; | ||
dma-names = "offload0-rx"; | ||
trigger-sources = <&ad4052>; | ||
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#address-cells = <0x1>; | ||
#size-cells = <0x0>; | ||
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ad4052: ad4052@0 { | ||
compatible = "adi,ad4052"; | ||
reg = <0>; | ||
vdd-supply = <&adc_vdd>; | ||
vio-supply = <&adc_vio>; | ||
spi-max-frequency = <31250000>; | ||
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#trigger-source-cells = <0>; | ||
pwms = <&adc_trigger 0 10000 0>; | ||
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interrupt-parent = <&gpio0>; | ||
interrupts = <86 IRQ_TYPE_EDGE_RISING>, | ||
<87 IRQ_TYPE_EDGE_FALLING>; | ||
interrupt-names = "gp0", "gp1"; | ||
cnv-gpios = <&gpio0 88 GPIO_ACTIVE_HIGH>; | ||
}; | ||
}; | ||
}; |
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