SPI Engine: add intel script

docs/library/spi_engine/tutorial.rst

@@ -68,7 +68,7 @@ SPI Engine hierarchy instantiation
 
 The SPI Engine can be implemented in two ways, either by placing and connecting
 each IP individually or by using the function provided by the
-:git-hdl:`library/spi_engine/scripts/spi_engine.tcl` script.
+:git-hdl:`library/spi_engine/scripts/spi_engine_xilinx.tcl` script.
 
 Using the script ensures that the correct connections are being made and that
 the IP cores will receive the correct parameter configuration since certain
@@ -103,7 +103,7 @@ Configuration tcl code and result below:
 
 .. code:: tcl
 
-   source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl
+   source $ad_hdl_dir/library/spi_engine/scripts/spi_engine_xilinx.tcl
 
    set data_width    32
    set async_spi_clk 1

docs/user_guide/ip_cores/use_adi_ips.rst

@@ -158,11 +158,11 @@ In order to use it into your own project, you will have to add all of its compon
 For this example, the code shown here is from the ad4630_fmc project:
 :git-hdl:`projects/ad4630_fmc/common/ad463x_bd.tcl`
 
-Let's start with sourcing the spi_engine.tcl script inside your ``<project>_db.tcl``.
+Let's start with sourcing the spi_engine_xilinx.tcl script inside your ``<project>_db.tcl``.
 
 .. code:: tcl
 
-   source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl
+   source $ad_hdl_dir/library/spi_engine/scripts/spi_engine_xilinx.tcl
 
 The SPI engine has 4 modules: execution, interconnect, regmap and offload.
 

library/spi_engine/scripts/spi_engine_intel.tcl

@@ -0,0 +1,99 @@
+###############################################################################
+## Copyright (C) 2025 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIBSD
+###############################################################################
+
+proc spi_engine_create {{name "spi_engine"}
+                        {axi_clk}
+                        {axi_reset}
+                        {spi_clk}
+                        {data_width 32}
+                        {async_spi_clk 1}
+                        {num_cs 1}
+                        {num_sdi 1}
+                        {num_sdo 1}
+                        {sdi_delay 0}
+                        {echo_sclk 0}
+                        {sdo_streaming 0}
+                        {cmd_mem_addr_width 4}
+                        {data_mem_addr_width 4}
+                        {sdi_fifo_addr_width 5}
+                        {sdo_fifo_addr_width 5}
+                        {sync_fifo_addr_width 4}
+                        {cmd_fifo_addr_width 4}} {
+
+  set execution "${name}_execution"
+  set axi_regmap "${name}_axi_regmap"
+  set offload "${name}_offload"
+  set interconnect "${name}_interconnect"
+
+  add_instance $execution spi_engine_execution
+  set_instance_parameter_value $execution {NUM_OF_CS} $num_cs
+  set_instance_parameter_value $execution {DATA_WIDTH} $data_width
+  set_instance_parameter_value $execution {NUM_OF_SDI} $num_sdi
+  set_instance_parameter_value $execution {SDI_DELAY} $sdi_delay
+  set_instance_parameter_value $execution {ECHO_SCLK} $echo_sclk
+  set_instance_parameter_value $execution {SDO_DEFAULT} 1
+
+  add_instance $axi_regmap axi_spi_engine
+  set_instance_parameter_value $axi_regmap {ASYNC_SPI_CLK} $async_spi_clk
+  set_instance_parameter_value $axi_regmap {DATA_WIDTH}    $data_width
+  set_instance_parameter_value $axi_regmap {MM_IF_TYPE}    {0}
+  set_instance_parameter_value $axi_regmap {NUM_OF_SDI}    $num_sdi
+  set_instance_parameter_value $axi_regmap {NUM_OFFLOAD}   {1}
+  set_instance_parameter_value $axi_regmap {OFFLOAD0_CMD_MEM_ADDRESS_WIDTH} $cmd_mem_addr_width
+  set_instance_parameter_value $axi_regmap {OFFLOAD0_SDO_MEM_ADDRESS_WIDTH} $data_mem_addr_width
+  set_instance_parameter_value $axi_regmap {SDI_FIFO_ADDRESS_WIDTH}         $sdi_fifo_addr_width
+  set_instance_parameter_value $axi_regmap {SDO_FIFO_ADDRESS_WIDTH}         $sdo_fifo_addr_width
+  set_instance_parameter_value $axi_regmap {SYNC_FIFO_ADDRESS_WIDTH}        $sync_fifo_addr_width
+  set_instance_parameter_value $axi_regmap {CMD_FIFO_ADDRESS_WIDTH}         $cmd_fifo_addr_width
+
+  add_instance $offload spi_engine_offload
+  set_instance_parameter_value $offload {ASYNC_TRIG}    {0}
+  set_instance_parameter_value $offload {ASYNC_SPI_CLK} 0
+  set_instance_parameter_value $offload {DATA_WIDTH}    $data_width
+  set_instance_parameter_value $offload {NUM_OF_SDI}    $num_sdi
+  set_instance_parameter_value $offload {SDO_STREAMING} $sdo_streaming
+  set_instance_parameter_value $offload {CMD_MEM_ADDRESS_WIDTH} $cmd_mem_addr_width
+  set_instance_parameter_value $offload {SDO_MEM_ADDRESS_WIDTH} $data_mem_addr_width
+
+  add_instance $interconnect spi_engine_interconnect
+  set_instance_parameter_value $interconnect {DATA_WIDTH} $data_width
+  set_instance_parameter_value $interconnect {NUM_OF_SDI} $num_sdi
+
+  # clocks
+  add_connection $axi_clk $axi_regmap.s_axi_clock
+  add_connection $spi_clk $axi_regmap.if_spi_clk
+  add_connection $spi_clk $execution.if_clk
+  add_connection $spi_clk $interconnect.if_clk
+  add_connection $spi_clk $offload.if_ctrl_clk
+  add_connection $spi_clk $offload.if_spi_clk
+
+  # resets
+  add_connection $axi_reset $axi_regmap.s_axi_reset
+  add_connection $axi_regmap.if_spi_resetn $execution.if_resetn
+  add_connection $axi_regmap.if_spi_resetn $interconnect.if_resetn
+  add_connection $axi_regmap.if_spi_resetn $offload.if_spi_resetn
+
+  # interfaces
+  add_connection $interconnect.m_cmd $execution.cmd
+  add_connection $execution.sdi_data $interconnect.m_sdi
+  add_connection $interconnect.m_sdo $execution.sdo_data
+  add_connection $execution.sync $interconnect.m_sync
+  add_connection $axi_regmap.cmd $interconnect.s1_cmd
+  add_connection $interconnect.s1_sdi $axi_regmap.sdi_data
+  add_connection $axi_regmap.sdo_data $interconnect.s1_sdo
+  add_connection $interconnect.s1_sync $axi_regmap.sync
+  add_connection $offload.cmd $interconnect.s0_cmd
+  add_connection $interconnect.s0_sdi  $offload.sdi_data
+  add_connection $offload.sdo_data $interconnect.s0_sdo
+  add_connection $interconnect.s0_sync $offload.sync
+  add_connection $offload.m_interconnect_ctrl $interconnect.s_interconnect_ctrl
+  add_connection $offload.ctrl_cmd_wr       $axi_regmap.offload0_cmd
+  add_connection $offload.ctrl_sdo_wr       $axi_regmap.offload0_sdo
+  add_connection $offload.if_ctrl_enable    $axi_regmap.if_offload0_enable
+  add_connection $offload.if_ctrl_enabled   $axi_regmap.if_offload0_enabled
+  add_connection $offload.if_ctrl_mem_reset $axi_regmap.if_offload0_mem_reset
+  add_connection $offload.status_sync       $axi_regmap.offload_sync
+
+}

library/spi_engine/scripts/spi_engine.tcl → library/spi_engine/scripts/spi_engine_xilinx.tcl

@@ -3,7 +3,21 @@
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 
-proc spi_engine_create {{name "spi_engine"} {data_width 32} {async_spi_clk 1} {num_cs 1} {num_sdi 1} {num_sdo 1} {sdi_delay 0} {echo_sclk 0} {sdo_streaming 0} {cmd_mem_addr_width 4} {data_mem_addr_width 4} {sdi_fifo_addr_width 5} {sdo_fifo_addr_width 5} {sync_fifo_addr_width 4} {cmd_fifo_addr_width 4}} {
+proc spi_engine_create {{name "spi_engine"}
+                        {data_width 32}
+                        {async_spi_clk 1}
+                        {num_cs 1}
+                        {num_sdi 1}
+                        {num_sdo 1}
+                        {sdi_delay 0}
+                        {echo_sclk 0}
+                        {sdo_streaming 0}
+                        {cmd_mem_addr_width 4}
+                        {data_mem_addr_width 4}
+                        {sdi_fifo_addr_width 5}
+                        {sdo_fifo_addr_width 5}
+                        {sync_fifo_addr_width 4}
+                        {cmd_fifo_addr_width 4}} {
   puts "echo_sclk: $echo_sclk"
 
   create_bd_cell -type hier $name
@@ -39,6 +53,7 @@ proc spi_engine_create {{name "spi_engine"} {data_width 32} {async_spi_clk 1} {n
   ad_ip_parameter $execution CONFIG.ECHO_SCLK $echo_sclk
 
   ad_ip_instance axi_spi_engine $axi_regmap
+  ad_ip_parameter $axi_regmap CONFIG.MM_IF_TYPE 0
   ad_ip_parameter $axi_regmap CONFIG.DATA_WIDTH $data_width
   ad_ip_parameter $axi_regmap CONFIG.NUM_OFFLOAD 1
   ad_ip_parameter $axi_regmap CONFIG.NUM_OF_SDI $num_sdi

library/spi_engine/spi_engine_execution/spi_engine_execution_hw.tcl

@@ -20,8 +20,9 @@ ad_ip_parameter DEFAULT_SPI_CFG INTEGER 0
 ad_ip_parameter DEFAULT_CLK_DIV INTEGER 0
 ad_ip_parameter DATA_WIDTH INTEGER 8
 ad_ip_parameter NUM_OF_SDI INTEGER 1
-ad_ip_parameter SDI_DELAY INTEGER 0
 ad_ip_parameter SDO_DEFAULT INTEGER 0
+ad_ip_parameter ECHO_SCLK INTEGER 0
+ad_ip_parameter SDI_DELAY INTEGER 0
 
 proc p_elaboration {} {
 

projects/ad4052_ardz/common/ad4052_bd.tcl

@@ -1,13 +1,13 @@
 ###############################################################################
-## Copyright (C) 2024 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2024-2025 Analog Devices, Inc. All rights reserved.
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 
 create_bd_port -dir O adc_cnv
 create_bd_port -dir I adc_gp1_n
 create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_engine_rtl:1.0 adc_spi
 
-source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl
+source $ad_hdl_dir/library/spi_engine/scripts/spi_engine_xilinx.tcl
 
 set data_width    32
 set async_spi_clk 1

projects/ad4052_ardz/common/ad4052_qsys.tcl

@@ -11,36 +11,6 @@ set_instance_parameter_value axi_dmac_0 {CYCLIC} {0}
 set_instance_parameter_value axi_dmac_0 {DMA_DATA_WIDTH_SRC} {32}
 set_instance_parameter_value axi_dmac_0 {DMA_DATA_WIDTH_DEST} {128}
 
-# axi_spi_engine
-
-add_instance axi_spi_engine_0 axi_spi_engine
-set_instance_parameter_value axi_spi_engine_0 {ASYNC_SPI_CLK} {1}
-set_instance_parameter_value axi_spi_engine_0 {DATA_WIDTH} {32}
-set_instance_parameter_value axi_spi_engine_0 {MM_IF_TYPE} {0}
-set_instance_parameter_value axi_spi_engine_0 {NUM_OF_SDI} {1}
-set_instance_parameter_value axi_spi_engine_0 {NUM_OFFLOAD} {1}
-
-# spi_engine_execution
-
-add_instance spi_engine_execution_0 spi_engine_execution
-set_instance_parameter_value spi_engine_execution_0 {DATA_WIDTH} {32}
-set_instance_parameter_value spi_engine_execution_0 {NUM_OF_SDI} {1}
-set_instance_parameter_value spi_engine_execution_0 {SDI_DELAY} {0}
-
-# spi_engine_interconnect
-
-add_instance spi_engine_interconnect_0 spi_engine_interconnect
-set_instance_parameter_value spi_engine_interconnect_0 {DATA_WIDTH} {32}
-set_instance_parameter_value spi_engine_interconnect_0 {NUM_OF_SDI} {1}
-
-# spi_engine_offload
-
-add_instance spi_engine_offload_0 spi_engine_offload
-set_instance_parameter_value spi_engine_offload_0 {ASYNC_TRIG} {1}
-set_instance_parameter_value spi_engine_offload_0 {ASYNC_SPI_CLK} {0}
-set_instance_parameter_value spi_engine_offload_0 {DATA_WIDTH} {32}
-set_instance_parameter_value spi_engine_offload_0 {NUM_OF_SDI} {1}
-
 # axi_pwm_gen
 
 add_instance pwm_trigger axi_pwm_gen
@@ -87,6 +57,26 @@ set_connection_parameter_value spi_clk_pll.reconfig_to_pll/spi_clk_pll_reconfig.
 set_connection_parameter_value spi_clk_pll.reconfig_to_pll/spi_clk_pll_reconfig.reconfig_to_pll startPortLSB {0}
 set_connection_parameter_value spi_clk_pll.reconfig_to_pll/spi_clk_pll_reconfig.reconfig_to_pll width {0}
 
+# spi engine
+source $ad_hdl_dir/library/spi_engine/scripts/spi_engine_intel.tcl
+
+set spi_engine_hier spi_ad4052
+
+set data_width 32
+set async_spi_clk 1
+set num_cs 1
+set num_sdi 1
+set num_sdo 1
+set sdi_delay 0
+set echo_sclk 0
+set sdo_streaming 0
+
+set axi_clk sys_clk.clk
+set axi_reset sys_clk.clk_reset
+set spi_clk spi_clk_pll.outclk0
+
+spi_engine_create $spi_engine_hier $axi_clk $axi_reset $spi_clk $data_width $async_spi_clk $num_cs $num_sdi $num_sdo $sdi_delay $echo_sclk $sdo_streaming
+set_instance_parameter_value ${spi_engine_hier}_offload {ASYNC_TRIG} {1}
 # exported interface
 
 add_interface adc_spi_sclk    clock source
@@ -95,27 +85,21 @@ add_interface adc_spi_sdo     conduit end
 add_interface adc_spi_cs      conduit end
 add_interface adc_drdy        conduit end
 
-set_interface_property adc_spi_sclk     EXPORT_OF spi_engine_execution_0.if_sclk
-set_interface_property adc_spi_sdi      EXPORT_OF spi_engine_execution_0.if_sdi
-set_interface_property adc_spi_sdo      EXPORT_OF spi_engine_execution_0.if_sdo
-set_interface_property adc_spi_cs       EXPORT_OF spi_engine_execution_0.if_cs
-set_interface_property adc_drdy_trigger EXPORT_OF spi_engine_offload_0.if_trigger
+set_interface_property adc_spi_sclk     EXPORT_OF ${spi_engine_hier}_execution.if_sclk
+set_interface_property adc_spi_sdi      EXPORT_OF ${spi_engine_hier}_execution.if_sdi
+set_interface_property adc_spi_sdo      EXPORT_OF ${spi_engine_hier}_execution.if_sdo
+set_interface_property adc_spi_cs       EXPORT_OF ${spi_engine_hier}_execution.if_cs
+set_interface_property adc_drdy_trigger EXPORT_OF ${spi_engine_hier}_offload.if_trigger
 set_interface_property adc_cnv          EXPORT_OF pwm_trigger.if_pwm_0
 
 # clocks
 
 add_connection sys_clk.clk spi_clk_pll.refclk
 add_connection sys_clk.clk spi_clk_pll_reconfig.mgmt_clk
-add_connection sys_clk.clk axi_spi_engine_0.s_axi_clock
 add_connection sys_clk.clk axi_dmac_0.s_axi_clock
 add_connection sys_clk.clk pwm_trigger.s_axi_clock
 
 add_connection spi_clk_pll.outclk0 pwm_trigger.if_ext_clk
-add_connection spi_clk_pll.outclk0 spi_engine_execution_0.if_clk
-add_connection spi_clk_pll.outclk0 spi_engine_interconnect_0.if_clk
-add_connection spi_clk_pll.outclk0 axi_spi_engine_0.if_spi_clk
-add_connection spi_clk_pll.outclk0 spi_engine_offload_0.if_ctrl_clk
-add_connection spi_clk_pll.outclk0 spi_engine_offload_0.if_spi_clk
 add_connection spi_clk_pll.outclk0 axi_dmac_0.if_s_axis_aclk
 
 add_connection sys_dma_clk.clk axi_dmac_0.m_dest_axi_clock
@@ -124,47 +108,19 @@ add_connection sys_dma_clk.clk axi_dmac_0.m_dest_axi_clock
 
 add_connection sys_clk.clk_reset spi_clk_pll.reset
 add_connection sys_clk.clk_reset spi_clk_pll_reconfig.mgmt_reset
-add_connection sys_clk.clk_reset axi_spi_engine_0.s_axi_reset
 add_connection sys_clk.clk_reset axi_dmac_0.s_axi_reset
 add_connection sys_clk.clk_reset pwm_trigger.s_axi_reset
 
-add_connection axi_spi_engine_0.if_spi_resetn spi_engine_execution_0.if_resetn
-add_connection axi_spi_engine_0.if_spi_resetn spi_engine_interconnect_0.if_resetn
-add_connection axi_spi_engine_0.if_spi_resetn spi_engine_offload_0.if_spi_resetn
-
 add_connection sys_dma_clk.clk_reset axi_dmac_0.m_dest_axi_reset
 
 # interfaces
 
-add_connection spi_engine_interconnect_0.m_cmd spi_engine_execution_0.cmd
-add_connection spi_engine_execution_0.sdi_data spi_engine_interconnect_0.m_sdi
-add_connection spi_engine_interconnect_0.m_sdo spi_engine_execution_0.sdo_data
-add_connection spi_engine_execution_0.sync spi_engine_interconnect_0.m_sync
-
-add_connection axi_spi_engine_0.cmd spi_engine_interconnect_0.s1_cmd
-add_connection spi_engine_interconnect_0.s1_sdi axi_spi_engine_0.sdi_data
-add_connection axi_spi_engine_0.sdo_data spi_engine_interconnect_0.s1_sdo
-add_connection spi_engine_interconnect_0.s1_sync axi_spi_engine_0.sync
-
-add_connection spi_engine_offload_0.cmd spi_engine_interconnect_0.s0_cmd
-add_connection spi_engine_interconnect_0.s0_sdi spi_engine_offload_0.sdi_data
-add_connection spi_engine_offload_0.sdo_data spi_engine_interconnect_0.s0_sdo
-add_connection spi_engine_interconnect_0.s0_sync spi_engine_offload_0.sync
-add_connection spi_engine_offload_0.m_interconnect_ctrl spi_engine_interconnect_0.s_interconnect_ctrl
-
-add_connection spi_engine_offload_0.ctrl_cmd_wr       axi_spi_engine_0.offload0_cmd
-add_connection spi_engine_offload_0.ctrl_sdo_wr       axi_spi_engine_0.offload0_sdo
-add_connection spi_engine_offload_0.if_ctrl_enable    axi_spi_engine_0.if_offload0_enable
-add_connection spi_engine_offload_0.if_ctrl_enabled   axi_spi_engine_0.if_offload0_enabled
-add_connection spi_engine_offload_0.if_ctrl_mem_reset axi_spi_engine_0.if_offload0_mem_reset
-add_connection spi_engine_offload_0.status_sync       axi_spi_engine_0.offload_sync
-
-add_connection spi_engine_offload_0.offload_sdi axi_dmac_0.s_axis
+add_connection ${spi_engine_hier}_offload.offload_sdi axi_dmac_0.s_axis
 
 # cpu interconnects
 
 ad_cpu_interconnect 0x00020000 axi_dmac_0.s_axi
-ad_cpu_interconnect 0x00030000 axi_spi_engine_0.s_axi
+ad_cpu_interconnect 0x00030000 ${spi_engine_hier}_axi_regmap.s_axi
 ad_cpu_interconnect 0x00040000 pwm_trigger.s_axi
 ad_cpu_interconnect 0x00050000 spi_clk_pll_reconfig.mgmt_avalon_slave
 
@@ -175,4 +131,4 @@ ad_dma_interconnect axi_dmac_0.m_dest_axi
 #interrupts
 
 ad_cpu_interrupt 4 axi_dmac_0.interrupt_sender
-ad_cpu_interrupt 5 axi_spi_engine_0.interrupt_sender
+ad_cpu_interrupt 5 ${spi_engine_hier}_axi_regmap.interrupt_sender

projects/ad4052_ardz/coraz7s/Makefile

@@ -1,5 +1,5 @@
 ####################################################################################
-## Copyright (c) 2018 - 2024 Analog Devices, Inc.
+## Copyright (c) 2018 - 2025 Analog Devices, Inc.
 ### SPDX short identifier: BSD-1-Clause
 ## Auto-generated, do not modify!
 ####################################################################################
@@ -11,7 +11,7 @@ M_DEPS += ../../scripts/adi_pd.tcl
 M_DEPS += ../../common/coraz7s/coraz7s_system_ps7.tcl
 M_DEPS += ../../common/coraz7s/coraz7s_system_constr.xdc
 M_DEPS += ../../common/coraz7s/coraz7s_system_bd.tcl
-M_DEPS += ../../../library/spi_engine/scripts/spi_engine.tcl
+M_DEPS += ../../../library/spi_engine/scripts/spi_engine_xilinx.tcl
 M_DEPS += ../../../library/common/ad_iobuf.v
 
 LIB_DEPS += axi_clkgen