Versal: Add JESD204 support for GTM transceivers

[bluncan]

PR Description

This PR adds support for JESD204 while using the GTM transceivers.
The gearbox modules written for intel have been moved to jesd204_common so that we can reuse them on Xilinx as well.
Because the GTM's don't have an internal gearbox and the default datapath when using JESD204C is 64 bits, there are two clocking options for the gearbox:

• we generate the required LR / 66 frequency clock in the JESD phy with some clk_wizards (external_link_clk = 0)
• we have the required LR / 66 frequency clock from somewhere else (e.g. externally or we route it from the ODIV port of the reference clock IBUFDS_GTE5) and we connect it to the JESD phy (external_link_clk = 1)

Both JESD204B and JESD204C are working in simulation but have not yet been tested in HW due to the lack of boards that export the GTMs to the FMC connectors.

PR Type

• Bug fix (change that fixes an issue)
• New feature (change that adds new functionality)
• Breaking change (has dependencies in other repos or will cause CI to fail)
• Documentation

PR Checklist

• I have followed the code style guidelines
• I have performed a self-review of changes
• I have compiled all hdl projects and libraries affected by this PR
• I have tested in hardware affected projects, at least on relevant boards
• I have commented my code, at least hard-to-understand parts
• I have signed off all commits from this PR
• I have updated the documentation (wiki pages, ReadMe files, Copyright etc)
• I have not introduced new Warnings/Critical Warnings on compilation
• I have added new hdl testbenches or updated existing ones