Fix timing issues on FMCOMMS2 and AD9081/VCU118 #1909

phlfm · 2025-09-09T20:35:47Z

⚠️ Warning - these changes have not been tested on the corresponding hardware / setup / boards!

PR Description

This PR addresses timing violations observed across multiple projects following the upgrade to Vivado 2025.1, without requiring any HDL modifications.

After the upgrade, most designs exhibited hold violations, likely due to Vivado's aggressive optimization for setup timing. This behavior appears to shorten certain paths excessively, inadvertently introducing hold issues. While invoking phys_opt_design post-route helped resolve some violations automatically, it was not consistently effective, particularly in congested regions where rerouting options were limited.

To mitigate this, the Congestion_SpreadLogic_high strategy was adopted (alternatively _medium or _low depending on design needs). This approach encourages a more distributed placement of logic, which not only alleviates congestion but can also accelerate implementation due to the relatively low resource utilization. Although this spreading may introduce setup timing challenges, a subsequent phys_opt_design pass (or two) has proven highly effective at resolving them.

By spreading the logic and reducing congestion, Vivado gains greater flexibility during post-route optimization, improving its ability to correct HOLD violations without manual intervention.

Change log

implemented scripts/auto_timing_fix.tcl
improvements to projects/scripts/adi_project_xilinx.tcl
- added ADI_MAX_THREADS so the trade-off between speed and RAM usage can be adjusted
- added post place and route script flag
- added documentation for other flags
fixed timing issues in fmcomms2 with 2025.1 toolchain without hdl changes
- project presented hold timing violations on vivado 2025.1
- "phys_opt_design -hold_fix" resolved it for most variations but not for all of them
- changed implementation strategy to spread placement on board to make hold timing easier to resolve
- now all projects finish successfully after the auto fix script runs
- no HDL changes were made
fixed timing for ad9081 on vcu118 for specific make parameters
- presented setup timing violations
- use of "spread high" strategy solved issues without need of ATF or HDL changes

PR Type

Bug fix (change that fixes an issue)
New feature (change that adds new functionality)
Breaking change (has dependencies in other repos or will cause CI to fail)
Documentation

PR Checklist

I have followed the code style guidelines
I have performed a self-review of changes
I have compiled all hdl projects and libraries affected by this PR
I have tested in hardware affected projects, at least on relevant boards
I have commented my code, at least hard-to-understand parts
I have signed off all commits from this PR
I have updated the documentation (wiki pages, ReadMe files, Copyright etc)
I have not introduced new Warnings/Critical Warnings on compilation
I have added new hdl testbenches or updated existing ones

CLAassistant · 2025-09-09T20:35:57Z

All committers have signed the CLA.

projects/fmcomms2/zc702/system_project.tcl

projects/fmcomms2/zc706/system_project.tcl

projects/fmcomms2/zcu102/system_project.tcl

projects/fmcomms2/zed/system_project.tcl

scripts/auto_timing_fix.tcl

Signed-off-by: Pedro Mendonca <Pedro.Mendonca@analog.com>

…script Signed-off-by: Pedro Mendonca <Pedro.Mendonca@analog.com>

…Logic_high Signed-off-by: Pedro Mendonca <Pedro.Mendonca@analog.com>

Signed-off-by: Pedro Mendonca <Pedro.Mendonca@analog.com>

phlfm · 2025-09-10T13:46:11Z

Split into more atomic commits as requested by @acostina

phlfm · 2025-09-15T16:03:29Z

RetriggerCI

LBFFilho · 2025-09-18T15:03:23Z

projects/scripts/adi_project_xilinx.tcl

+# Additional configuration flags are:
+# - ADI_EXTRACT_PORTS - If set, extracts port properties from a predefined list
+#   of IPs into 'ports_properties.txt'.
+# - ADI_GENERATE_BIN - If set, generates a binary bitstream file (.bin)
+#   in addition to the .xsa hardware platform.
+# - ADI_GENERATE_UTILIZATION - If set, generates CSV and log files detailing
+#   resource utilization for the design and specific IPs.
+# - ADI_GENERATE_XPA - If set, runs a Xilinx Power Analysis (XPA) and generates
+#   a summary report.
+# - ADI_MAX_OOC_JOBS - Specifies the number of parallel jobs to use for
+#   Out-of-Context (OOC) synthesis.
+# - ADI_MAX_THREADS - Specifies the maximum number of threads for Vivado
+#   operations. Default value is 8.
+# - ADI_NO_BITSTREAM_COMPRESSION - If set, disables compression of the final
+#   bitstream file.
+# - ADI_POST_ROUTE_SCRIPT - Specifies the path to a Tcl script to be executed
+#   after the routing design step.
+# - ADI_POWER_OPTIMIZATION - If set to 1, enables power optimization during the
+#   implementation run.
+# - ADI_PROJECT_DIR - Specifies a base directory for output files such as logs
+#   and reports.
+# - ADI_SKIP_SYNTHESIS - If set, the entire procedure will exit before starting
+#   synthesis.
+# - ADI_USE_OOC_SYNTHESIS - If set to 1, launches synthesis for OOC IP modules
+#   in parallel.


It would be nice to have all of those described on the rst doc (build_hdl.rst), not all of them are there

LBFFilho

Looks good and everything builds fine, it would be nice to test it on hardware before merging.

caosjr · 2025-09-19T14:04:38Z

scripts/auto_timing_fix.tcl

+    if {$final_wns >= 0} {
+        puts "INFO: ATF: auto timing fix SUCCESS after ${attempt} attempts - final WNS is ${final_wns} ns."
+    } elseif {$final_wns <= $ADI_AUTOFIX_WNS_THRESHOLD} {
+        puts "WARNING: ATF: WNS (${wns} ns) excedes threshold (${ADI_AUTOFIX_WNS_THRESHOLD} ns). Automatic fix aborted."


typo: exceeds.

puts "WARNING: ATF: WNS (${wns} ns) exceeds threshold (${ADI_AUTOFIX_WNS_THRESHOLD} ns). Automatic fix aborted."

Signed-off-by: Pedro Mendonca <Pedro.Mendonca@analog.com>

caosjr · 2025-09-19T14:10:53Z

projects/scripts/adi_project_xilinx.tcl

Typo line 321: existing.

Add source files to an existing project.

caosjr · 2025-09-19T14:18:21Z

projects/scripts/adi_project_xilinx.tcl

I know it is not related to this commit, but maybe it could be added as well. It is not necessary the elseif in line 332, just an else satisfies the filter for constrs_1 and sources_1.

if {[string range $pfile [expr 1 + [string last . $pfile]] end] == "xdc"} { add_files -norecurse -fileset constrs_1 $pfile } else { add_files -norecurse -fileset sources_1 $pfile }

caosjr · 2025-09-19T17:36:28Z

system_bd.tcl scripts are not using your BOARD_NAME variable.

bia1708 · 2025-09-22T08:23:33Z

RetriggerCI

Signed-off-by: Pedro Mendonca <Pedro.Mendonca@analog.com>

- use less space in jenkins due to checkpoints being large in size - status of ATF execution is visible by checkpoint file name Signed-off-by: Pedro Mendonca <Pedro.Mendonca@analog.com>

Signed-off-by: Pedro Mendonca <Pedro.Mendonca@analog.com>

phlfm · 2025-09-26T12:16:26Z

RetriggerCI

phlfm self-assigned this Sep 9, 2025

phlfm requested review from AndrDragomir, AndreiGrozav, FilipG24, IuliaCMoldovan, LBFFilho, PopPaul2021, acostina, bluncan, gastmaier, podgori and sarpadi as code owners September 9, 2025 20:35

IuliaCMoldovan added the bug label Sep 10, 2025

IuliaCMoldovan changed the title ~~fix timing issues on fmcomms2 and ad9081 vcu118~~ Fix timing issues on FMCOMMS2 and AD9081/VCU118 Sep 10, 2025

IuliaCMoldovan requested changes Sep 10, 2025

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phlfm added 9 commits September 10, 2025 10:28

implemented scripts/auto_timing_fix.tcl

1489474

Signed-off-by: Pedro Mendonca <Pedro.Mendonca@analog.com>

scripts/adi_project_xilinx.tcl: added ADI_POST_ROUTE_SCRIPT flag

87f8044

Signed-off-by: Pedro Mendonca <Pedro.Mendonca@analog.com>

scripts/adi_project_xilinx.tcl: added documentation for run flags

beda6b0

Signed-off-by: Pedro Mendonca <Pedro.Mendonca@analog.com>

projects/fmcomms2: auto timing fix added as post route script

f2d6cf0

Signed-off-by: Pedro Mendonca <Pedro.Mendonca@analog.com>

projects/fmcomms2: change strategy to Congestion_SpreadLogic_high

c485f42

Signed-off-by: Pedro Mendonca <Pedro.Mendonca@analog.com>

projects/fmcomms2: refactor system_project.tcl as Factory Method

ebdd90f

Signed-off-by: Pedro Mendonca <Pedro.Mendonca@analog.com>

projects/ad9081_fmca_ebz/vcu118: auto timing fix added as post route …

711ecfb

…script Signed-off-by: Pedro Mendonca <Pedro.Mendonca@analog.com>

projects/ad9081_fmca_ebz/vcu118: change strategy to Congestion_Spread…

e96efa8

…Logic_high Signed-off-by: Pedro Mendonca <Pedro.Mendonca@analog.com>

projects/fmcomms2: update copyright header

2cc0018

Signed-off-by: Pedro Mendonca <Pedro.Mendonca@analog.com>

phlfm force-pushed the fix_timing_fmcomms2_and_ad9081 branch from ba373d6 to 2cc0018 Compare September 10, 2025 13:42

phlfm requested a review from IuliaCMoldovan September 10, 2025 13:45

LBFFilho reviewed Sep 18, 2025

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LBFFilho reviewed Sep 19, 2025

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caosjr reviewed Sep 19, 2025

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move build docs from adi_project_xilinx.tcl to build_hdl.rst

d9f795f

Signed-off-by: Pedro Mendonca <Pedro.Mendonca@analog.com>

caosjr reviewed Sep 19, 2025

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projects/scripts/adi_project_xilinx.tcl

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caosjr Sep 19, 2025 •

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Typo line 321: existing.

Add source files to an existing project.

caosjr reviewed Sep 19, 2025

View reviewed changes

phlfm added 13 commits September 25, 2025 16:25

projects/scripts/adi_project_xilinx.tcl: fixed typo

dcd4b10

Signed-off-by: Pedro Mendonca <Pedro.Mendonca@analog.com>

projects/scripts/adi_project_xilinx.tcl: removed redundant elsif

dbddf29

Signed-off-by: Pedro Mendonca <Pedro.Mendonca@analog.com>

scripts/auto_timing_fix.tcl: fixed typo

19827c5

Signed-off-by: Pedro Mendonca <Pedro.Mendonca@analog.com>

projects/fmcomms5: added ATF as post-route script

ba61f00

Signed-off-by: Pedro Mendonca <Pedro.Mendonca@analog.com>

projects/fmcomms5: refactor system_project.tcl as Factory Method

8c4ef13

Signed-off-by: Pedro Mendonca <Pedro.Mendonca@analog.com>

scripts/auto_timing_fix.tcl: removed checkpoint for each iteration

4d9f047

- use less space in jenkins due to checkpoints being large in size - status of ATF execution is visible by checkpoint file name Signed-off-by: Pedro Mendonca <Pedro.Mendonca@analog.com>

projects/fmcomms5: change strategy to Congestion_SpreadLogic_high

7a59b76

Signed-off-by: Pedro Mendonca <Pedro.Mendonca@analog.com>

projects/daq2: refactor system_project.tcl as Factory Method

175a371

Signed-off-by: Pedro Mendonca <Pedro.Mendonca@analog.com>

projects/daq2: auto timing fix added as post route script

73d1d5d

Signed-off-by: Pedro Mendonca <Pedro.Mendonca@analog.com>

projects/daq2: removing trailing ws from system_project.tcl

0c62f70

Signed-off-by: Pedro Mendonca <Pedro.Mendonca@analog.com>

projects/daq2: change strategy to Congestion_SpreadLogic_high

734c73a

Signed-off-by: Pedro Mendonca <Pedro.Mendonca@analog.com>

projects/daq2: updating copyright header

ac0b807

Signed-off-by: Pedro Mendonca <Pedro.Mendonca@analog.com>

projects/fmcomms5: updating copyright header

7fed80d

Signed-off-by: Pedro Mendonca <Pedro.Mendonca@analog.com>

phlfm requested a review from StancaPop as a code owner September 25, 2025 20:02

IuliaCMoldovan approved these changes Oct 10, 2025

View reviewed changes

IuliaCMoldovan requested review from sarpadi and removed request for sarpadi October 10, 2025 08:52

Fix timing issues on FMCOMMS2 and AD9081/VCU118 #1909

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Fix timing issues on FMCOMMS2 and AD9081/VCU118 #1909

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