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@FilipG24 FilipG24 commented Aug 7, 2025

PR Description

Remove the Data Offload Bypass FIFO when synthesis parameter HAS_BYPASS is set to value '0'. By default this parameter has value '1'.

By removing the DO Bypass FIFO certain timing paths are optimized because there is not need to have this additional logic during design runtime!

PR Type

  • Bug fix (change that fixes an issue)
  • New feature (change that adds new functionality)
  • Breaking change (has dependencies in other repos or will cause CI to fail)
  • Documentation

PR Checklist

  • I have followed the code style guidelines
  • I have performed a self-review of changes
  • I have compiled all hdl projects and libraries affected by this PR
  • I have tested in hardware affected projects, at least on relevant boards
  • I have commented my code, at least hard-to-understand parts
  • I have signed off all commits from this PR
  • I have updated the documentation (wiki pages, ReadMe files, Copyright etc)
  • I have not introduced new Warnings/Critical Warnings on compilation
  • I have added new hdl testbenches or updated existing ones

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CLAassistant commented Aug 7, 2025

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All committers have signed the CLA.

@FilipG24 FilipG24 requested a review from bluncan August 7, 2025 13:49
bluncan
bluncan previously approved these changes Aug 7, 2025
Signed-off-by: Filip Gherman <filip.gherman@analog.com>
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4 participants