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JESD204C: Add FEC and pipeline stages #1871

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JESD204C: Add FEC and pipeline stages #1871

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bluncan
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@bluncan bluncan commented Aug 7, 2025

PR Description

Adds FEC support for JESD204C.
This PR also adds some optional pipeline stages that should help us meet timing at higher lanerates.

PR Type

  • Bug fix (change that fixes an issue)
  • New feature (change that adds new functionality)
  • Breaking change (has dependencies in other repos or will cause CI to fail)
  • Documentation

PR Checklist

  • I have followed the code style guidelines
  • I have performed a self-review of changes
  • I have compiled all hdl projects and libraries affected by this PR
  • I have tested in hardware affected projects, at least on relevant boards
  • I have commented my code, at least hard-to-understand parts
  • I have signed off all commits from this PR
  • I have updated the documentation (wiki pages, ReadMe files, Copyright etc)
  • I have not introduced new Warnings/Critical Warnings on compilation
  • I have added new hdl testbenches or updated existing ones

@bluncan bluncan force-pushed the dev_jesd_improvements branch from 84dfafc to 319bfa0 Compare August 7, 2025 13:46
Matthew.Blanton and others added 10 commits August 7, 2025 16:48
@bluncan
Changes to help with timing
ac4a7fd
@bluncan
library: jesd204: jesd204_rx_lane_64b: Fixed crc mismatch
d85cc20 
Signed-off-by: Bogdan Luncan <bogdan.luncan@analog.com>
@bluncan
library: jesd204: jesd204_tx: Fixed pipeline for 8b10b
79de919 
Signed-off-by: Bogdan Luncan <bogdan.luncan@analog.com>
@bluncan
library: common: ad_mem_dist: Rename and add registered output
316c9c3 
Signed-off-by: Bogdan Luncan <bogdan.luncan@analog.com>
@bluncan
library: jesd204: fec: Update licenses and cleanup
c7c55d6 
Signed-off-by: Bogdan Luncan <bogdan.luncan@analog.com>
@bluncan
library: jesd204: axi_jesd204: Bump core version
41bafd9 
Signed-off-by: Bogdan Luncan <bogdan.luncan@analog.com>
@bluncan
library: jesd204: jesd204_fec_decode: Register ad_mem output
bcd0353 
Signed-off-by: bluncan <bogdan.luncan@analog.com>
@bluncan
library: jesd204: tb: Make tb work with modelsim
6bba191 
Signed-off-by: bluncan <bogdan.luncan@analog.com>
@bluncan
library: jesd204: Add missing .v dependencies
e0a34eb 
Signed-off-by: Bogdan Luncan <bogdan.luncan@analog.com>
@bluncan
library: jesd204: ad_ip_jesd204_tpl_adc: Add optional pipeline stage …
3513345 
…inside deframer

Signed-off-by: Bogdan Luncan <bogdan.luncan@analog.com>
@bluncan bluncan force-pushed the dev_jesd_improvements branch from 319bfa0 to 3513345 Compare August 7, 2025 13:49
@sarpadi
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sarpadi commented Oct 8, 2025

@RetriggerCI

@bia1708
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bia1708 commented Oct 9, 2025

RetriggerCI

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@bluncan @sarpadi @bia1708