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projects: ad9084_ebz: Add readme file
Signed-off-by: Bogdan Luncan <bogdan.luncan@analog.com>
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‎projects/ad9084_ebz/README.md‎

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# AD9084-EBZ HDL Project
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- Evaluation board product page: [EVAL-AD9084](https://www.analog.com/eval-ad9084)
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- HDL project documentation: https://analogdevicesinc.github.io/hdl/projects/ad9084_ebz/index.html
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- Evaluation board VADJ range: 1.2V - 3.3V
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## Supported parts
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| Part name | Description |
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|------------------------------------------------|--------------------------------------------------------------|
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| [AD9084 (Apollo MxFE)](https://www.analog.com/ad9084) | Quad, 16-Bit 28GSPS RF DAC and Quad 12-Bit, 20GSPS RF ADC |
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## Building the project
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Please enter the folder for the FPGA carrier you want to use and read the README.md.

‎projects/ad9084_ebz/fm87/README.md‎

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<!-- no_no_os -->
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# AD9084-EBZ/FM87 HDL Project
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- VADJ with which it was tested in hardware: 1.2V
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## Building the project
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The parameters configurable through the `make` command, can be found below, as well as in the **system_project.tcl** file; it contains the default configuration.
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:warning: **When changing the default configuration, the system_constr.sdc constraints should be updated as well!**
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```
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cd projects/ad9084_ebz/fm87
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make
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```
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All of the RX/TX link modes can be found in the [AD9084 data sheet](https://www.analog.com/media/en/technical-documentation/user-guides/eval-ad9084-ug-2326.pdf). We offer support for only a few of them.
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The overwritable parameters from the environment are:
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- JESD_MODE : Used link layer encoder mode
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- 64B66B - 64b66b link layer defined in JESD 204C
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- 8B10B - 8b10b link layer defined in JESD 204B
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-
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- REF_CLK_RATE : Reference clock frequency in MHz, should be Lane Rate / 66 for JESD204C or Lane Rate / 40 for JESD204B
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- DEVICE_CLK_RATE : Device clock frequency in MHz, usually the same as REF_CLK_RATE but it can vary based on the JESD configuration
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- ENABLE_HSCI : If set, adds and enables the HSCI core in the design
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- RX_LANE_RATE : Lane rate of the Rx link ( Apollo to FPGA )
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- TX_LANE_RATE : Lane rate of the Tx link ( FPGA to Apollo )
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- [RX/TX]_JESD_M : Number of converters per link
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- [RX/TX]_JESD_L : Number of lanes per link
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- [RX/TX]_JESD_NP : Number of bits per sample
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- [RX/TX]_NUM_LINKS : Number of links - only when ASYMMETRIC_A_B_MODE = 0
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- [RX/TX]_KS_PER_CHANNEL: Number of samples stored in internal buffers in kilosamples per converter (M)

‎projects/ad9084_ebz/vck190/README.md‎

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<!-- no_no_os -->
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# AD9084-EBZ/VCK190 HDL Project
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- VADJ with which it was tested in hardware: 1.5V
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## Building the project
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The parameters configurable through the `make` command, can be found below, as well as in the **system_project.tcl** file; it contains the default configuration.
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```
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cd projects/ad9084_ebz/vck190
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make
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```
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All of the RX/TX link modes can be found in the [AD9084 data sheet](https://www.analog.com/media/en/technical-documentation/user-guides/eval-ad9084-ug-2326.pdf). We offer support for only a few of them.
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The overwritable parameters from the environment are:
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- JESD_MODE : Used link layer encoder mode
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- 64B66B - 64b66b link layer defined in JESD 204C
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- 8B10B - 8b10b link layer defined in JESD 204B
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-
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- REF_CLK_RATE : Reference clock frequency in MHz, should be Lane Rate / 66 for JESD204C or Lane Rate / 40 for JESD204B
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- HSCI_ENABLE : If set, adds and enables the HSCI core in the design
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- RX_LANE_RATE : Lane rate of the Rx link ( Apollo to FPGA )
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- TX_LANE_RATE : Lane rate of the Tx link ( FPGA to Apollo )
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- [RX/TX]_JESD_M : Number of converters per link
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- [RX/TX]_JESD_L : Number of lanes per link
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- [RX/TX]_JESD_NP : Number of bits per sample
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- [RX/TX]_NUM_LINKS : Number of links - only when ASYMMETRIC_A_B_MODE = 0
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- [RX/TX]_KS_PER_CHANNEL: Number of samples stored in internal buffers in kilosamples per converter (M)
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- ASYMMETRIC_A_B_MODE : When set, each Apollo side has its own JESD link
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- RX_B_LANE_RATE : Lane rate of the Rx link ( Apollo to FPGA ) for B side
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- TX_B_LANE_RATE : Lane rate of the Tx link ( FPGA to Apollo ) for B side
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- [RX/TX]_B_JESD_M : Number of converters per link for B side
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- [RX/TX]_B_JESD_L : Number of lanes per link for B side
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- [RX/TX]_B_JESD_NP : Number of bits per sample for B side
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- [RX/TX]_B_KS_PER_CHANNEL: Number of samples stored in internal buffers in kilosamples per converter (M) for B side

‎projects/ad9084_ebz/vcu118/README.md‎

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<!-- no_no_os -->
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# AD9084-EBZ/VCU118 HDL Project
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- VADJ with which it was tested in hardware: 1.8V
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## Building the project
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The parameters configurable through the `make` command, can be found below, as well as in the **system_project.tcl** file; it contains the default configuration.
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```
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cd projects/ad9084_ebz/vcu118
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make
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```
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All of the RX/TX link modes can be found in the [AD9084 data sheet](https://www.analog.com/media/en/technical-documentation/user-guides/eval-ad9084-ug-2326.pdf). We offer support for only a few of them.
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The overwritable parameters from the environment are:
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- JESD_MODE : Used link layer encoder mode
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- 64B66B - 64b66b link layer defined in JESD 204C
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- 8B10B - 8b10b link layer defined in JESD 204B
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-
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- REF_CLK_RATE : Reference clock frequency in MHz, should be Lane Rate / 66 for JESD204C or Lane Rate / 40 for JESD204B
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- RX_LANE_RATE : Lane rate of the Rx link ( Apollo to FPGA )
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- TX_LANE_RATE : Lane rate of the Tx link ( FPGA to Apollo )
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- [RX/TX]_JESD_M : Number of converters per link
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- [RX/TX]_JESD_L : Number of lanes per link
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- [RX/TX]_JESD_NP : Number of bits per sample
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- [RX/TX]_NUM_LINKS : Number of links - only when ASYMMETRIC_A_B_MODE = 0
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- [RX/TX]_KS_PER_CHANNEL: Number of samples stored in internal buffers in kilosamples per converter (M)
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- ASYMMETRIC_A_B_MODE : When set, each Apollo side has its own JESD link
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- RX_B_LANE_RATE : Lane rate of the Rx link ( Apollo to FPGA ) for B side
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- TX_B_LANE_RATE : Lane rate of the Tx link ( FPGA to Apollo ) for B side
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- [RX/TX]_B_JESD_M : Number of converters per link for B side
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- [RX/TX]_B_JESD_L : Number of lanes per link for B side
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- [RX/TX]_B_JESD_NP : Number of bits per sample for B side
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- [RX/TX]_B_KS_PER_CHANNEL: Number of samples stored in internal buffers in kilosamples per converter (M) for B side

‎projects/ad9084_ebz/vpk180/README.md‎

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<!-- no_no_os -->
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# AD9084-EBZ/VPK180 HDL Project
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- VADJ with which it was tested in hardware: 1.5V
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## Building the project
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The parameters configurable through the `make` command, can be found below, as well as in the **system_project.tcl** file; it contains the default configuration.
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```
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cd projects/ad9084_ebz/vpk180
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make
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```
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All of the RX/TX link modes can be found in the [AD9084 data sheet](https://www.analog.com/media/en/technical-documentation/user-guides/eval-ad9084-ug-2326.pdf). We offer support for only a few of them.
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The overwritable parameters from the environment are:
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- JESD_MODE : Used link layer encoder mode
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- 64B66B - 64b66b link layer defined in JESD 204C
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- 8B10B - 8b10b link layer defined in JESD 204B
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-
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- REF_CLK_RATE : Reference clock frequency in MHz, should be Lane Rate / 66 for JESD204C or Lane Rate / 40 for JESD204B
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- HSCI_ENABLE : If set, adds and enables the HSCI core in the design
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- RX_LANE_RATE : Lane rate of the Rx link ( Apollo to FPGA )
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- TX_LANE_RATE : Lane rate of the Tx link ( FPGA to Apollo )
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- [RX/TX]_JESD_M : Number of converters per link
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- [RX/TX]_JESD_L : Number of lanes per link
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- [RX/TX]_JESD_NP : Number of bits per sample
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- [RX/TX]_NUM_LINKS : Number of links - only when ASYMMETRIC_A_B_MODE = 0
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- [RX/TX]_KS_PER_CHANNEL: Number of samples stored in internal buffers in kilosamples per converter (M)
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- ASYMMETRIC_A_B_MODE : When set, each Apollo side has its own JESD link
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- RX_B_LANE_RATE : Lane rate of the Rx link ( Apollo to FPGA ) for B side
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- TX_B_LANE_RATE : Lane rate of the Tx link ( FPGA to Apollo ) for B side
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- [RX/TX]_B_JESD_M : Number of converters per link for B side
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- [RX/TX]_B_JESD_L : Number of lanes per link for B side
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- [RX/TX]_B_JESD_NP : Number of bits per sample for B side
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- [RX/TX]_B_KS_PER_CHANNEL: Number of samples stored in internal buffers in kilosamples per converter (M) for B side

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