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projects: ad9084_ebz: versal: Update constraints to read the lane rate automatically
Signed-off-by: Bogdan Luncan <bogdan.luncan@analog.com>
1 parent d46119d commit 1faecf5

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+9
-58
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2 files changed

+9
-58
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‎projects/ad9084_ebz/vck190/timing_constr.tcl‎

Lines changed: 4 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -3,18 +3,17 @@
33
### SPDX short identifier: ADIBSD
44
###############################################################################
55

6-
source ../../../scripts/adi_env.tcl
76
# Primary clock definitions
87

98
# Set clocks depending on the requested LANE_RATE paramter from the util_adxcvr block
109
# Maximum values for Link clock:
1110
# 204B - 15.5 Gbps /40 = 387.5MHz
1211
# 204C - 24.75 Gbps /66 = 375MHz
13-
set jesd_mode [get_env_param JESD_MODE 64B66B]
14-
set link_mode [expr {$jesd_mode=="64B66B"?2:1}]
12+
set jesd_mode [dict get [get_property IP_LR0_SETTINGS [get_cells i_system_wrapper/system_i/jesd204_phy/gt_bridge_ip_0/inst]] INTERNAL_PRESET]
13+
set link_mode [expr {$jesd_mode=="JESD204_64B66B" ? 2:1}]
1514

16-
set rx_lane_rate [get_env_param RX_LANE_RATE 20.625]
17-
set tx_lane_rate [get_env_param TX_LANE_RATE 20.625]
15+
set rx_lane_rate [dict get [get_property IP_LR0_SETTINGS [get_cells i_system_wrapper/system_i/jesd204_phy/gt_bridge_ip_0/inst]] RX_LINE_RATE]
16+
set tx_lane_rate [dict get [get_property IP_LR0_SETTINGS [get_cells i_system_wrapper/system_i/jesd204_phy/gt_bridge_ip_0/inst]] TX_LINE_RATE]
1817

1918
set rx_link_clk [expr $rx_lane_rate*1000/[expr {$link_mode==2?66:40}]]
2019
set tx_link_clk [expr $tx_lane_rate*1000/[expr {$link_mode==2?66:40}]]
@@ -32,29 +31,6 @@ set tx_device_clk [expr $tx_link_clk*$tx_ll_width/$tx_tpl_width]
3231
set rx_device_clk_period [expr 1000/$rx_device_clk]
3332
set tx_device_clk_period [expr 1000/$tx_device_clk]
3433

35-
set ASYMMETRIC_A_B_MODE [get_env_param ASYMMETRIC_A_B_MODE 0]
36-
37-
if {$ASYMMETRIC_A_B_MODE} {
38-
set rx_b_lane_rate [get_env_param RX_B_LANE_RATE 20.625]
39-
set tx_b_lane_rate [get_env_param TX_B_LANE_RATE 20.625]
40-
41-
set rx_b_link_clk [expr $rx_b_lane_rate*1000/[expr {$link_mode==2?66:40}]]
42-
set tx_b_link_clk [expr $tx_b_lane_rate*1000/[expr {$link_mode==2?66:40}]]
43-
44-
set rx_b_link_clk_period [expr 1000/$rx_b_link_clk]
45-
set tx_b_link_clk_period [expr 1000/$tx_b_link_clk]
46-
47-
set rx_b_ll_width [get_property DATA_PATH_WIDTH [get_cells i_system_wrapper/system_i/axi_apollo_rx_b_jesd/rx/inst]]
48-
set tx_b_ll_width [get_property DATA_PATH_WIDTH [get_cells i_system_wrapper/system_i/axi_apollo_tx_b_jesd/tx/inst]]
49-
set rx_b_tpl_width [get_property TPL_DATA_PATH_WIDTH [get_cells i_system_wrapper/system_i/axi_apollo_rx_b_jesd/rx/inst]]
50-
set tx_b_tpl_width [get_property TPL_DATA_PATH_WIDTH [get_cells i_system_wrapper/system_i/axi_apollo_tx_b_jesd/tx/inst]]
51-
52-
set rx_b_device_clk [expr $rx_b_link_clk*$rx_b_ll_width/$rx_b_tpl_width]
53-
set tx_b_device_clk [expr $tx_b_link_clk*$tx_b_ll_width/$tx_b_tpl_width]
54-
set rx_b_device_clk_period [expr 1000/$rx_b_device_clk]
55-
set tx_b_device_clk_period [expr 1000/$tx_b_device_clk]
56-
}
57-
5834
# refclk and refclk_replica are connect to the same source on the PCB
5935
# Set reference clock to same frequency as the link clock,
6036
# this will ease the XCVR out clocks propagation calculation.

‎projects/ad9084_ebz/vpk180/timing_constr.tcl‎

Lines changed: 5 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -3,19 +3,17 @@
33
### SPDX short identifier: ADIBSD
44
###############################################################################
55

6-
source ../../../scripts/adi_env.tcl
76
# Primary clock definitions
87

98
# Set clocks depending on the requested LANE_RATE paramter from the util_adxcvr block
109
# Maximum values for Link clock:
1110
# 204B - 15.5 Gbps /40 = 387.5MHz
1211
# 204C - 24.75 Gbps /66 = 375MHz
13-
set jesd_mode [get_env_param JESD_MODE 64B66B]
14-
set link_mode [expr {$jesd_mode=="64B66B"?2:1}]
15-
# set link_mode 1
12+
set jesd_mode [dict get [get_property IP_LR0_SETTINGS [get_cells i_system_wrapper/system_i/jesd204_phy/gt_bridge_ip_0/inst]] INTERNAL_PRESET]
13+
set link_mode [expr {$jesd_mode=="JESD204_64B66B" ? 2:1}]
1614

17-
set rx_lane_rate [get_env_param RX_LANE_RATE 20.625]
18-
set tx_lane_rate [get_env_param TX_LANE_RATE 20.625]
15+
set rx_lane_rate [dict get [get_property IP_LR0_SETTINGS [get_cells i_system_wrapper/system_i/jesd204_phy/gt_bridge_ip_0/inst]] RX_LINE_RATE]
16+
set tx_lane_rate [dict get [get_property IP_LR0_SETTINGS [get_cells i_system_wrapper/system_i/jesd204_phy/gt_bridge_ip_0/inst]] TX_LINE_RATE]
1917

2018
set rx_link_clk [expr $rx_lane_rate*1000/[expr {$link_mode==2?66:40}]]
2119
set tx_link_clk [expr $tx_lane_rate*1000/[expr {$link_mode==2?66:40}]]
@@ -33,34 +31,11 @@ set tx_device_clk [expr $tx_link_clk*$tx_ll_width/$tx_tpl_width]
3331
set rx_device_clk_period [expr 1000/$rx_device_clk]
3432
set tx_device_clk_period [expr 1000/$tx_device_clk]
3533

36-
set ASYMMETRIC_A_B_MODE [get_env_param ASYMMETRIC_A_B_MODE 0]
37-
38-
if {$ASYMMETRIC_A_B_MODE} {
39-
set rx_b_lane_rate [get_env_param RX_B_LANE_RATE 20.625]
40-
set tx_b_lane_rate [get_env_param TX_B_LANE_RATE 20.625]
41-
42-
set rx_b_link_clk [expr $rx_b_lane_rate*1000/[expr {$link_mode==2?66:40}]]
43-
set tx_b_link_clk [expr $tx_b_lane_rate*1000/[expr {$link_mode==2?66:40}]]
44-
45-
set rx_b_link_clk_period [expr 1000/$rx_b_link_clk]
46-
set tx_b_link_clk_period [expr 1000/$tx_b_link_clk]
47-
48-
set rx_b_ll_width [get_property DATA_PATH_WIDTH [get_cells i_system_wrapper/system_i/axi_apollo_rx_b_jesd/rx/inst]]
49-
set tx_b_ll_width [get_property DATA_PATH_WIDTH [get_cells i_system_wrapper/system_i/axi_apollo_tx_b_jesd/tx/inst]]
50-
set rx_b_tpl_width [get_property TPL_DATA_PATH_WIDTH [get_cells i_system_wrapper/system_i/axi_apollo_rx_b_jesd/rx/inst]]
51-
set tx_b_tpl_width [get_property TPL_DATA_PATH_WIDTH [get_cells i_system_wrapper/system_i/axi_apollo_tx_b_jesd/tx/inst]]
52-
53-
set rx_b_device_clk [expr $rx_b_link_clk*$rx_b_ll_width/$rx_b_tpl_width]
54-
set tx_b_device_clk [expr $tx_b_link_clk*$tx_b_ll_width/$tx_b_tpl_width]
55-
set rx_b_device_clk_period [expr 1000/$rx_b_device_clk]
56-
set tx_b_device_clk_period [expr 1000/$tx_b_device_clk]
57-
}
58-
5934
# refclk and refclk_replica are connect to the same source on the PCB
6035
# Set reference clock to same frequency as the link clock,
6136
# this will ease the XCVR out clocks propagation calculation.
6237
# TODO: this restricts RX_LANE_RATE=TX_LANE_RATE
63-
create_clock -name refclk0 -period $rx_link_clk_period [get_ports ref_clk_p]
38+
create_clock -name refclk0 -period $rx_link_clk_period [get_ports ref_clk_p[0]]
6439

6540
# device clock
6641
create_clock -name rx_device_clk -period $rx_device_clk_period [get_ports clk_m2c_p[0]]

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