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1 | 1 | Glossary
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2 | 2 | ========
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3 | 3 |
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| -| .. rubric:: Term | .. rubric:: Definition | |
6 |
| -| :name: term | :name: definition | |
7 |
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| -+-----------------------+----------------------------------------------+ |
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10 |
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11 |
| -| Amaranth | An open-source toolchain for developing hardware | |
12 |
| -| | based on synchronous digital logic using the | |
13 |
| -| | Python programming language | |
14 |
| -+===================+==================================================+ |
15 |
| -| ASIC | Application-specific integrated circuit | |
16 |
| -+-------------------+--------------------------------------------------+ |
17 |
| -| Domain | A group of logic elements | |
18 |
| -+-------------------+--------------------------------------------------+ |
19 |
| -| DUT | Device under test | |
20 |
| -+-------------------+--------------------------------------------------+ |
21 |
| -| Finite state | A mathematical model for a system that has a | |
22 |
| -| machine | limited number of conditional states of being | |
23 |
| -+-------------------+--------------------------------------------------+ |
24 |
| -| FPGA | Field Programmable Gate Array — a design, | |
25 |
| -| | blueprint, template | |
26 |
| -+-------------------+--------------------------------------------------+ |
27 |
| -| HDL | Hardware definition language | |
28 |
| -+-------------------+--------------------------------------------------+ |
29 |
| -| IC | Integrated circuit | |
30 |
| -+-------------------+--------------------------------------------------+ |
31 |
| -| Logic gate | A basic circuit with at least one — usually more | |
32 |
| -| | — inputs and one output | |
33 |
| -+-------------------+--------------------------------------------------+ |
34 |
| -| LUT | Look up table | |
35 |
| -+-------------------+--------------------------------------------------+ |
36 |
| -| MCU | Microcontroller unit | |
37 |
| -+-------------------+--------------------------------------------------+ |
38 |
| -| Propagation delay | The time it takes for a signal to move from | |
39 |
| -| | source to destination | |
40 |
| -+-------------------+--------------------------------------------------+ |
41 |
| -| RTL | Register transfer language | |
42 |
| -+-------------------+--------------------------------------------------+ |
| 4 | +**Amaranth** |
| 5 | +| An open-source toolchain that uses the Python programming language. |
| 6 | +| Amaranth makes developing hardware definitions, based on synchronous |
| 7 | + digital logic, more intuitive by using the popular Python programming |
| 8 | + language. The toolchain consists of the Amaranth language, the |
| 9 | + standard library, the simulator, and the build system, covering all |
| 10 | + steps of a typical FPGA development workflow. |
| 11 | + |
| 12 | +**ASIC (Application-specific integrated circuit)** |
| 13 | +| A non-standard integrated circuit chip made for a specific task or |
| 14 | + product. |
| 15 | +| The term *application* refers to the function the circuit will |
| 16 | + perform, not to a software application. |
| 17 | +| ASICs can be configured to be more power efficient and have better |
| 18 | + performance than an off-the-shelf general purpose integrated circuit. |
| 19 | + However, unlike FPGAs, ASICs cannot be reprogrammed and are expensive |
| 20 | + to produce so design and testing are critical to the success of ASIC |
| 21 | + development. |
| 22 | +| Rather than designing and building them from the ground up, ASICs can |
| 23 | + be created by interconnecting functional components from cell |
| 24 | + libraries. The resulting system can then be verified via simulation. |
| 25 | + |
| 26 | +**CLB (Configurable logic block)** |
| 27 | +| The basic repeating logic block on an FPGA, the purpose of CLBs is to |
| 28 | + implement combinational and sequential logic on an FPGA. |
| 29 | +| Each FPGA contains many logic blocks that are surrounded by a system |
| 30 | + of programmable interconnects (I/O blocks), called a fabric, that |
| 31 | + routes signals between the CLBs. |
| 32 | +| The three essential components of a logic block are flip-flops, LUTs, |
| 33 | + and multiplexers. |
| 34 | + |
| 35 | +**Clock signal** |
| 36 | +| An electronic logic signal that oscillates between a high and a low |
| 37 | + state at a constant frequency, used to synchronise the actions of |
| 38 | + digital circuits |
| 39 | +| The clock signal enters the FPGA system through a single physical |
| 40 | + connecting pin and is responsible for the speed at which an FPGA can |
| 41 | + run and process data. |
| 42 | +| A wave at a particular frequency is distributed across the FPGA to |
| 43 | + produce a synchronised response from all the flip-flops in the design. |
| 44 | + Performance of the system will be affected if the flip-flops do not |
| 45 | + all receive the clock signal at the same time. It’s possible to use |
| 46 | + more than one clock in an FPGA design but it is complicated and |
| 47 | + requires a degree of skill in circuit design. |
| 48 | + |
| 49 | +**DUT (Device under test)** |
| 50 | +| A manufactured device that is being tested for performance and |
| 51 | + proficiency. |
| 52 | +| The device fails testing as soon the first out-of-tolerance value is |
| 53 | + identified. The aim is to ensure damaged devices don’t enter the |
| 54 | + market. |
| 55 | + |
| 56 | +**Finite state machine** |
| 57 | +| A mathematical model describing a system with a limited number of |
| 58 | + conditional states of being. |
| 59 | +| A finite state machine reads a series of inputs. For each input, it |
| 60 | + will transition to a different state. Each state specifies which state |
| 61 | + to transition to next, for the given input. When the processing is |
| 62 | + complete, a ‘then’ action is taken. The abstract machine can process |
| 63 | + only one state at a time. |
| 64 | +| This approach enables engineers to study and test each input and |
| 65 | + output scenario. |
| 66 | + |
| 67 | +**Flip-flop** |
| 68 | +| The basic memory element for storing a single bit of information. |
| 69 | +| An edge-triggered device, it reacts to the edge of a pulse. Flip-flops |
| 70 | + synchronise logic and save logical states between clock cycles within |
| 71 | + an FPGA circuit. On every rising or falling clock edge, a flip-flop |
| 72 | + latches the 1 or 0 (TRUE or FALSE) value on its input and holds that |
| 73 | + value constant until the next clock edge. |
| 74 | + |
| 75 | +**FPGA (Field Programmable Gate Array)** |
| 76 | +| A reconfigurable integrated circuit containing internal hardware |
| 77 | + blocks with user-programmable interconnects to create a customised |
| 78 | + application. |
| 79 | +| The device’s physical attributes are programmed using a hardware |
| 80 | + definition language. I /O blocks interface between the FPGA and |
| 81 | + external devices. |
| 82 | +| FPGAs combine speed, programmability, and flexibility: FPGAs don't |
| 83 | + jump between memory and programming in the way ASICSs and CPUs do, so |
| 84 | + storing and retrieving data is more efficient. In addition, they can |
| 85 | + process very large volumes of data by duplicating circuits and running |
| 86 | + them in parallel. |
| 87 | + |
| 88 | +**Hardware register** |
| 89 | +| Circuits, typically composed of flip flops, often with characteristics |
| 90 | + similar to memory and having additional hardware-related functions. |
| 91 | +| Hardware registers are used in the interface between software and |
| 92 | + peripherals. |
| 93 | + |
| 94 | +**HDL (Hardware description language)** |
| 95 | +| Hardware description languages describe the structure, behaviour, and |
| 96 | + timing of electronic circuits and digital logic circuits. |
| 97 | +| HDLs describe behavioural, register transfer, gate, and switch-level |
| 98 | + logic. Behavioural level logic enables the sequential execution of |
| 99 | + instructions; and register transfer logic enables the transfer of data |
| 100 | + between registers. These actions are driven by an explicit clock and |
| 101 | + gate level logic that defines the individual gate level logic. HDLs |
| 102 | + can also be used to simulate a circuit and verify its response. |
| 103 | + |
| 104 | +**IC (Integrated circuit)** |
| 105 | +| An integrated circuit is a computer chip that has an electronic |
| 106 | + circuit embedded in it. |
| 107 | +| The circuit is a small wafer, usually made of silicon, that can hold |
| 108 | + anywhere from hundreds to millions of transistors, resistors, and |
| 109 | + capacitors. These components can perform calculations and store data |
| 110 | + using either digital or analog technology. |
| 111 | +| Digital ICs use logic gates that work only with values of 1s and 0s. A |
| 112 | + low signal sent to a component on a digital IC will result in a value |
| 113 | + of 0, while a high signal creates a value of 1. |
| 114 | + |
| 115 | +**Logic gate** |
| 116 | +| An elementary building block of integrated circuits, logic gates |
| 117 | + perform logical operations on binary inputs and outputs. |
| 118 | +| Based on a Boolean function that computes TRUE or FALSE, each output |
| 119 | + is based on the input or combination of inputs supplied to it. |
| 120 | +| **LUT (Look up table)** |
| 121 | + |
| 122 | +| An elementary building block of integrated circuits, a LUT is a truth |
| 123 | + table that defines how combinatorial logic behaves: the output for |
| 124 | + every combination of inputs. |
| 125 | +| The computation is very fast because the function requires only a |
| 126 | + single memory lookup regardless of the complexity of the function. |
| 127 | + |
| 128 | +**MCU (Microcontroller unit)** |
| 129 | +| A compact integrated circuit designed to govern a specific operation |
| 130 | + in an embedded system. |
| 131 | +| An MCU typically comprises a processor unit, memory modules, |
| 132 | + communication interfaces, and peripherals. |
| 133 | + |
| 134 | +**Multiplexer** |
| 135 | +| A combinational logic circuit designed to switch one of several inputs |
| 136 | + through to a single common output by the application of a control |
| 137 | + signal. |
| 138 | +| A multiplexer makes it possible for several input signals to share one |
| 139 | + device or resource instead of having one device per input signal. They |
| 140 | + use high speed logic gates to switch digital or binary data through to |
| 141 | + a single output. |
| 142 | + |
| 143 | +**Propagation delay** |
| 144 | +| The time required to change the output from one logic state to another |
| 145 | + logic state after input is applied. |
| 146 | +| In simplified terms, the time it takes for a signal to move from |
| 147 | + source to destination. The timing begins when the input to a logic |
| 148 | + gate becomes stable and valid to change and ends when the output of |
| 149 | + that logic gate is stable and valid to change. |
| 150 | +| The propagation delay of a complete circuit is calculated by |
| 151 | + identifying the longest path of propagation delay from input to output |
| 152 | + and adding each propagation delay along the path. |
| 153 | + |
| 154 | +**RTL (Register transfer level)** |
| 155 | +| RTL is used to create high-level representations of a circuit, from |
| 156 | + which lower-level representations and wiring can be derived. |
| 157 | +| It models a synchronous digital circuit in terms of the flow of |
| 158 | + digital signals between hardware registers, and the logical operations |
| 159 | + performed on those signals. |
| 160 | + |
| 161 | +**Simulation** |
| 162 | +| A process in which a model of an electronic circuit is replicated and |
| 163 | + analysed to verify its functionality. |
| 164 | +| Simulation is an invaluable tool for ensuring a circuit works the way |
| 165 | + it was intended to by checking accuracy, capacity, and performance. It |
| 166 | + also enables designers to rapidly iterate designs and test them to |
| 167 | + find the optimal configuration. |
| 168 | + |
| 169 | +**SoC (System on Chip)** |
| 170 | +| An integrated circuit, containing all the circuitry and components an |
| 171 | + electronic system requires. |
| 172 | +| In contrast to a traditional computer system that is made up of many |
| 173 | + distinct components, an SoC integrates the required resources — CPU, |
| 174 | + memory interfaces, I/O devices, I/O interfaces, secondary storage |
| 175 | + interfaces — into a single chip. SoCs are typically built around a |
| 176 | + microprocessor, microcontroller, or specialised integrated circuit. |
| 177 | + This increases performance, reduces power consumption, and requires a |
| 178 | + smaller semiconductor die area. |
| 179 | + |
| 180 | +**Wave form** |
| 181 | +| A visual representation of the variation of a voltage or current over |
| 182 | + time. |
| 183 | +| Periodic waveforms vary at a given frequency, for example, the voltage |
| 184 | + or current of a signal is amplified or reduced to provide a clock |
| 185 | + signal for an FPGA. |
| 186 | +| Waveforms have three main characteristics: period, the length of time |
| 187 | + the waveform takes to repeat; frequency, the number of times the |
| 188 | + waveform repeats within a one second time period; and amplitude, the |
| 189 | + magnitude or intensity of the signal waveform measured in volts or |
| 190 | + amps. |
| 191 | +| The waveform of an electrical signal can be visualised in an |
| 192 | + oscilloscope or similar instrument that can capture and plot the |
| 193 | + variations in the signal. The square waveform is commonly used to |
| 194 | + represent digital information. |
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