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b449030
Revert "staging: board: disable as it breaks the build"
geertu Jun 17, 2015
c32b589
staging: board: Initialize staging board code earlier
geertu Jun 17, 2015
459fcc5
staging: board: Add support for translating hwirq to virq numbers
geertu Jun 17, 2015
9e01433
staging: board: kzm9d: Translate hwirq numbers to virq numbers
geertu Jun 17, 2015
368f99e
staging: board: Add support for devices with complex dependencies
geertu Jun 17, 2015
69d60bd
staging: board: armadillo800eva: Board staging for sh_mobile_lcdc_fb
geertu Jun 17, 2015
878c515
staging: make board support depend on OF_IRQ and CLKDEV_LOOKUP
Jun 20, 2015
72a560d
staging: board: Migrate away from __pm_genpd_name_add_device()
geertu Sep 8, 2015
d49e99c
ARM: dts: fix gpio-keys wakeup-source property
sudeep-holla Oct 16, 2015
98120c3
clockevents/drivers/sh_cmt: Only perform clocksource suspend/resume i…
geertu Dec 8, 2015
e4ed513
clkdev: use clk_hw internally
Dec 8, 2015
acc647f
clkdev: const-ify connection id to clk_add_alias()
Dec 8, 2015
e87d7a0
clkdev: get rid of redundant clk_add_alias() prototype in linux/clk.h
Dec 8, 2015
2df91b3
PM / Domains: Skip timings during syscore suspend/resume
geertu Dec 8, 2015
1354c8b
ARM: socfpga: dts: add cpu1-start-addr for Arria 10
Mar 10, 2015
03287b3
ARM: socfpga: dts: disable the sdmmc, and uart nodes in the base arria10
Mar 10, 2015
2ea2117
ARM: socfpga: dts: enable UART1 for the debug uart
Apr 2, 2015
b15528e
ARM: socfpga: dts: rename socdk board file to socdk_sdmmc
Mar 10, 2015
9a1dd9f
ARM: socfpga: dts: Add a clock node for sdmmc CIU
Apr 10, 2015
8cf2005
ARM: socfpga: dts: Add multicast bins and unicast filter entries
Apr 21, 2015
706b57d
ARM: socfpga: dts: Add tx-fifo-depth and rx-fifo-depth properties
Apr 21, 2015
9cb9bd1
ARM: socfpga: dts: add clocks to the Arria10 platform
Apr 2, 2015
3bb2c33
ARM: socfpga: Add support for UART1 debug uart for earlyprintk
Mar 9, 2015
54196ea
ARM: socfpga: remove the need to map uart_io_desc
Mar 10, 2015
82925a1
ARM: socfpga: dts: add the a9-scu node
May 12, 2015
5d6013e
ARM: socfpga: use of_iomap to map the SCU
May 12, 2015
cec1066
clk: socfpga: update clk.h so for Arria10 platform to use
May 20, 2015
f10f4d3
clk: socfpga: add a clock driver for the Arria 10 platform
May 20, 2015
6cb2ea9
ARM: socfpga: dts: add the a9-scu node for arria10
May 14, 2015
6cfc5f9
ARM: socfpga: dts: add enable-method property for cpu nodes
May 23, 2015
115503d
clk: of: helper for filling parent clock array and return num of parents
Jun 5, 2015
1b3ac35
clk: socfpga: make use of of_clk_parent_fill helper function
Jun 5, 2015
d00c922
ARM: socfpga: use CPU_METHOD_OF_DECLARE for socfpga_cyclone5
Jun 3, 2015
92f021a
ARM: socfpga: add CPU_METHOD_OF_DECLARE for Arria 10
Jun 3, 2015
a19c408
ARM: socfpga: dts: enable ethernet for Arria10 devkit
Jun 3, 2015
f9fdde3
ARM: socfpga: support suspend to ram
Jun 5, 2015
52f8884
ARM: dts: socfpga: enable the data and instruction prefetch for the l…
Jul 16, 2015
0d845d5
ARM: dts: socfpga: use stdout-path for chosen node
Jul 14, 2015
3cd5c4e
ARM: socfpga: add reset for the Arria 10 platform
Jul 20, 2015
535ee22
ARM: socfpga: dts: Correct the parent clock for l3_sp_clk and dbg_clk
Nov 20, 2013
cbff153
ARM: socfpga: dts: Fix gpio dts entry for the correct clock
May 29, 2014
36c83d2
ARM: socfpga: dts: add osc1 as a possible parent for dbg_base_clk
Jul 25, 2015
44bdecf
reset: socfpga: Update reset-socfpga to read the altr,modrst-offset p…
Jul 31, 2015
f6205ca
dt-bindings: Add reset manager offsets for Arria10
Jul 24, 2015
05052fd
ARM: socfpga: dts: add "altr,modrst-offset" property
Jul 24, 2015
cdbaffd
ARM: socfpga: dts: Add resets for EMACs on Arria10
Jul 24, 2015
69e4c35
clk: socfpga: Add a second parent option for the dbg_base_clk
Jul 25, 2015
4103b94
EDAC, altera: Generalize driver to use DT Memory size
Jun 4, 2015
aefc2c7
EDAC, altera: Refactor for Altera CycloneV SoC
Jun 4, 2015
7f7f650
EDAC, altera: Add Arria10 EDAC support
Jun 4, 2015
5ac03c2
arm: socfpga: dts: Add Arria10 SDRAM EDAC DTS support
Jun 4, 2015
1b3bdaa
EDAC, altera: Do not allow suspend when EDAC is enabled
Jun 5, 2015
9734be7
ARM: dts: socfpga: Add support of Terasic DE0 Atlas board
dwesterg Jul 8, 2015
702c16b
usage documentation for FPGA manager core
Oct 7, 2015
920db2b
fpga manager: add sysfs interface document
Oct 7, 2015
81abec8
add FPGA manager core
Oct 7, 2015
adc6d00
fpga manager: add driver for socfpga fpga manager
Oct 7, 2015
8e6bbc7
MAINTAINERS: add fpga manager framework
Oct 7, 2015
a4e3f37
ARM: socfpga_defconfig: enable fpga manager
Oct 13, 2015
834561c
ARM: socfpga: dts: add fpga manager
Oct 13, 2015
7da600f
nios2: Export get_cycles
herbertx Jun 9, 2015
69f89b4
nios2: check number of timer instances
Jun 24, 2015
55743ff
nios2/time: Migrate to new 'set-state' interface
vireshk Aug 18, 2015
8e07d3a
nios2: fixed variable imm16 to s16
Sep 4, 2015
22b8d5b
nios2: remove unused statistic counters
Sep 4, 2015
e0e52ab
nios2: Add Max10 device tree
Sep 8, 2015
d1f261f
nios2: add Max10 defconfig
Sep 8, 2015
7c7d190
nios2: Fix unused variable warning
Sep 30, 2015
17df245
nios2: Switch to generic __xchg()
Sep 30, 2015
ba7b34c
ARM: Add msi.h to Kbuild
Dec 9, 2015
460bf51
PCI: altera: Add Altera PCIe host controller driver
Dec 9, 2015
3033d76
PCI: altera: Add Altera PCIe MSI driver
Dec 9, 2015
b01d029
PCI: altera: Fix loop in tlp_read_packet()
Dec 9, 2015
88a10b5
PCI: altera: Fix Requester ID for config accesses
Dec 9, 2015
f6ea0da
PCI: altera: Check TLP completion status
Dec 9, 2015
86b6197
PCI: altera: Fix error when INTx is 4
Dec 9, 2015
d5e3a7d
ARM: socfpga: fix build error due to secondary_startup
Jun 11, 2015
09eed1b
Input: add support for ROHM BU21023/24 touchscreen
Sep 19, 2015
e164b88
Input: rohm_bu21023 - fix handling of retrying firmware update
dtor Jan 6, 2016
81a1a35
mtd: nand: support for Toshiba BENAND (Built-in ECC NAND)
ystk Oct 22, 2015
ef8c7ea
FogBugz #198256: Fix unnecessary USB overcurrent condition
May 22, 2014
c688a6f
FogBugz #91445: Fix intermittent data starvation for DMA on SD/MMC
Feb 12, 2013
89307da
FogBugz #142858: Fix intermittent SD/MMC RFS from not mounting
Aug 2, 2013
116234c
arm: socfpga: Enable spi and qspi driver for socfpga
Oct 16, 2012
eccc69a
FogBugz #79418: Add support for Denali NAND controller
Oct 22, 2012
2ccc028
FogBugz #97284: Update L2 cache settings
Jan 28, 2013
182baf3
FogBugz #106327: Use framework in drivers/base/soc.c for system id
Mar 14, 2013
acada69
FogBugz #103219: Turn on ARM errata for L2 cache
Feb 28, 2013
7956976
FogBugz #103239: Intermittent loss of ethernet transmission.
Apr 5, 2013
ef14165
FogBugz #102675: do not touch fpga bridge resets by default
Jul 16, 2013
613f6c9
FogBugz #143478: arch/arm: Move sysid from arch to drivers
Aug 12, 2013
f07d005
FogBugz #172665: Sample driver for DMA transfer to FPGA soft IP (FIFO)
Dec 13, 2013
053ea9d
FogBugz #184646: Turn on all peripheral clocks for a system reboot
Feb 18, 2014
8fb7cb8
FogBugz #193022: Fix warning for allmodconfig on socfpga_defconfig
Mar 24, 2014
85c0c7a
FogBugz #119719: Document Cadence QSPI Controller device tree bindings
Jul 24, 2013
b7e149a
FogBugz #99945-2: add gpio-dwapb driver to defconfig and dts
Mar 6, 2014
e8fe51c
FogBugz #194611: Configure I2C SDA and SCL parameters
altcrauer Apr 4, 2014
f5d895e
FogBugz #163905: Support Denali NAND driver on socfpga platform
Oct 28, 2013
370b32a
FogBugz #84276: lcd driver on i2c
Nov 29, 2012
eb20133
FogBugz #100586: Set lcd backlight brightness to max
Feb 15, 2013
0291065
FogBugz #102358: i2c newhaven lcd driver uses faulty hyphen
Feb 26, 2013
09a149f
tty: newhaven_lcd: Remove devinit and devexit
Jun 17, 2014
ae31fc5
FogBugz #107683: handle backspace better in lcd driver
Mar 21, 2013
e15d6a4
FogBugz #114479: load custom character for backslash
Apr 24, 2013
b0e0573
FogBugz #118160: support tilde character on newhaven lcd module
Apr 25, 2013
3b06052
FogBugz #125882: lcd module needs time to process commands.
May 23, 2013
e4853b7
FogBugz #101176: add sys entry to set lcd module brightness
May 24, 2013
d8e4d21
FogBugz #98100: designware i2c driver add speed mode in devtree
Jan 31, 2013
3ae178b
FogBugz #177284: add Altera VIP framebuffer driver
altcrauer May 10, 2013
52fb704
ARM: SOCFPGA: update socfpga_defconfig
Jun 16, 2014
12f76ed
mtd: denali: Need to read the have-hw-ecc-fixup property.
Jun 25, 2014
df933fc
FogBugz #138162: Add Altera hardware mutex driver
Jul 25, 2013
6792f80
FogBugz #143451: Fix mutex compatible string
Aug 5, 2013
e525e3c
FogBugz #144109: Remove extra lines from license header
Aug 7, 2013
7ff3f2c
FogBugz #178225: Add Altera interrupt latency counter driver
Feb 21, 2014
5d0012a
FogBugz #97184: Add Altera SYSID soft IP driver
Feb 5, 2013
bf59a5c
FogBugz #109717: Removed unused sysid driver from drivers/misc.
Mar 25, 2013
86c1fe6
FogBugz #143478: drivers/misc: Move sysid from arch to drivers
Aug 12, 2013
889af92
Add qspi for socfpga.dtsi
Aug 4, 2014
4058193
Set spi_master addr_width parameter in m25p80, needed by Cadence QSPI…
Aug 11, 2014
90e55e0
FogBugz #189684-2: dts part: clean up QSPI entries
Mar 11, 2014
9f7856a
mtd: m25p80: Add shutdown handler for m25p80 and spi-nor
Aug 12, 2014
cdabd6f
FogBugz #228949: Add CONFIG_MARVELL_PHY to socfpga_defconfig
Sep 4, 2014
adda681
FogBugz #229601: newhaven lcd: fix kbuild test robot warnings
Sep 5, 2014
f6d8871
FogBugz #240546: Move VIP driver into FB hardware folder
Oct 23, 2014
be0f19d
misc: hwmutex: replace devm_request_and_ioremap with devm_ioremap_res…
Oct 6, 2014
422fbe0
misc: sysid: replace devm_request_and_ioremap with devm_ioremap_and_r…
Oct 6, 2014
7a59c94
misc: ilc: replace devm_request_and_ioremap with devm_ioremap_and_res…
Oct 6, 2014
1b8be36
FogBugz #236669: Add a Kconfig for ILC driver
Oct 9, 2014
5f28b04
misc: hwmutex: use IS_ERR and PTR_ERR to check for error
Oct 14, 2014
e9a7b7c
misc: sysid: use IS_ERR and PTR_ERR to check for error
Oct 14, 2014
923cefe
reset: socfpga: use arch_initcall for early initialization
Oct 8, 2014
c10db8e
FogBugz #173183: L2 EDAC addition for Altera SOCFPGA.
Dec 13, 2013
c587bbf
FogBugz #173184: Add L2 EDAC error injection for testing.
Dec 18, 2013
69a8d30
FogBugz #178128: Conditionally enable L2 EDAC.
Jan 16, 2014
5eebd3c
FogBugz #173185: OCRAM ECC addition for Altera SOCFPGA.
Dec 19, 2013
556d22d
FogBugz #180994: Conditionally enable L2 cache ECC on startup
Jan 31, 2014
fbff948
FogBugz #179457: Abstract EDAC module triggers
Jan 23, 2014
d136c45
FogBugz #173188: Add OCRAM ECC Error Injection for testing.
Feb 10, 2014
1b94282
FogBugz #184650: Cleanup Altera license headers.
Feb 18, 2014
699d304
FogBugz #250531-1: fix l2 ECC enabling
Aug 27, 2014
0f5cc37
FogBugz #250531-2: DTS: Update SPI node to align with kernel.org
Dec 10, 2014
5574230
FogBugz #250531-3: socfpga_defconfig: Clean up socfpga_defconfig
Dec 9, 2014
0e56629
FogBugz #250531-4: DTS: Clean up cyclone5_socdk
Dec 10, 2014
d6a6599
FogBugz #250531-5: DTS: Clean up arria5_socdk
Dec 10, 2014
207c23d
TRCom NAND board device tree.
Oct 9, 2014
c0e63ef
FogBugz #261262: Cleanup of SPI device tree (3.18)
Feb 3, 2015
314b8c8
arm: cti: fix up cti pmu build
Feb 18, 2015
4285ae2
mfd: Altera Arria10 System Controller Implementation
Jan 9, 2015
666332e
gpio: Altera Arria10 System Controller - GPIO
Dec 22, 2014
c355724
hwmon: Altera Arria10 System Controller - HW Monitor
Dec 29, 2014
e409b11
reset: Altera Arria10 System Controller - Reset Controller
Dec 29, 2014
2b22ba0
arm: dts: Altera Arria10 System Controller Device Tree entries
Dec 22, 2014
6c5aa0e
FogBugz #270904-6: A10SyCon: Remove Arria10 Interrupts
Feb 25, 2015
889dc65
FogBugz #270904-8: Add support for n25q00aa QSPI chip on A10 devkit
Mar 5, 2015
7eaca3b
FogBugz #270904-9: Add qspi node for Arria10
Feb 17, 2015
1321f0f
FogBugz #270904-15: SPI: A10SYCON fixes for 3.18
Mar 9, 2015
8c6feaa
FogBugz #270904-16: A10SYCON: Enable GPIO & HWMON by default
Mar 10, 2015
6ac14c0
FogBugz #270904-19: arria10: device tree: add i2c peripherals
Mar 10, 2015
754c1f0
FogBugz #282531-1: Add "pwr-en" dts property to enable the PWREN bit
Mar 5, 2015
93d4d56
FogBugz #282531-2: add pwr-en to the arria10 dts board file
Mar 4, 2015
88ed50d
FogBugz #288024-2: Correct Micrel phy documentation for ksz90x1
Mar 31, 2015
578424c
FogBugz #288812-1: enable socfpga arria10 fpga manager
Mar 13, 2015
c81ae9f
FogBugz #288412: Add correct reset manager offsets for Arria10
Mar 25, 2015
4e48001
FogBugz #293560: v4.0 upgrade: update socfpga_defconfig
Apr 17, 2015
0f6d011
FogBugz #293560-1: A10SYCON: Cleanup and additions to hwmon
Mar 2, 2015
a7e1856
FogBugz #299928: arria10 swvp: add device tree
May 19, 2015
0ae68b1
FogBugz #294156: Enable watchdog on Arria10
May 29, 2015
4a28aad
FogBugz #298977: Add sys ID module to socfpga_defconfig
thloh May 14, 2015
e518104
mtd: spi-nor: Bindings for Cadence Quad SPI Flash Controller driver.
Mar 23, 2015
4b20a6d
mtd: spi-nor: Add driver for Cadence Quad SPI Flash Controller.
Mar 23, 2015
9d856f8
FogBugz #311020-1: qspi: update driver for v4.1
Jul 14, 2015
92e1f56
FogBugz #311020-2: qspi: dts: update the dts to use upstream qspi patch
Jul 14, 2015
eb618f2
FogBugz #311020-3: qspi: update socfpga_defconfig for v4.1
Jul 14, 2015
91ab880
FogBugz #311020-4: update altera_edac.h
Jul 15, 2015
0b52036
FogBugz #292777: Calibrate read_delay at runtime
Jul 15, 2015
87cc3f4
FogBugz #315701-1: add call to enable l2 edac for arria10
Aug 3, 2015
7000cbb
FogBugz #315701-2: add of_node_put for L2 ecc node
Aug 3, 2015
5dc06aa
FogBugz #315701-3: Add support for Arria10 L2 ECC
Aug 3, 2015
9ccd011
FogBugz #315701-4: add L2 cache EDAC entry for Arria10
Jul 29, 2015
24b23d0
FogBugz #315701-5: edit L2 cache ECC device tree documentation
Jul 29, 2015
f390388
FogBugz #315701-6: Add support for OCRAM ECC on arria10
Aug 3, 2015
b6348a5
FogBugz #315701-7: update ECC driver to support Arria10
Aug 3, 2015
9893702
FogBugz #315701-8: dts: add OCRAM EDAC entry
Jul 29, 2015
33080c7
FogBugz #315701-9: edit OCRAM ECC device tree documentation
Jul 29, 2015
ce77b42
FogBugz #315701-10: fix the ALTR_MAN_GRP_OCRAM_ECC_OFFSET define
Aug 6, 2015
e99a396
FogBugz #317771: Fix all the memory leaks
Aug 14, 2015
5ec7954
FogBugz #323286: fix up ecc for v4.2
Sep 29, 2015
515081c
FogBugz #316846-1: MSL: Add platform specific code to support NAND ECC
Aug 11, 2015
63422b3
FogBugz #316846-2: drivers portion of NAND ECC for Arria10
Aug 11, 2015
c922aad
FogBugz #316846-3: dts: add NAND EDAC entries for Arria 10
Aug 7, 2015
af86329
FogBugz #316846-4: docs: dts-bindings: add doc for Arria 10 NAND ECC
Aug 7, 2015
49971e8
FogBugz #332657-1: Stratix 10 Software Virtual Platform
yvanderv-altera Oct 28, 2015
18a1917
FogBugz #332657-2: Stratix 10 Software Virtual Platform
yvanderv-altera Feb 4, 2016
7d2e671
FogBugz #332657-3: Stratix 10 Software Virtual Platform
yvanderv-altera Oct 28, 2015
2d31b2a
FogBugz #331067: misc: altera_hwmutex: remove .owner
Oct 20, 2015
675d938
FogBugz #331066: misc: altera_hwmutex: remove redundant unused of_mat…
Oct 20, 2015
2e60ab8
arm64: dts: Add base stratix 10 dtsi
Aug 5, 2015
174ad2a
FogBugz #333771: fix boot from the openembedded initrd failure
yvanderv-altera Nov 4, 2015
d68aa29
FogBugz #334039: enable SMP for the Stratix10 SWVP
yvanderv-altera Nov 5, 2015
9263b73
FogBugz #334036: Fix qspi partitioning
Nov 5, 2015
a3aa57b
FogBugz #339844-2: Add NAND device tree for Arria10
Jul 7, 2015
86ce737
FogBugz #341071: Remove commit 973e60ecef962 to fix SPI1 interrupt
Dec 14, 2015
e99d550
ARM: dts: socfpga: add cap-sd-highspeed for SD/MMC node
Jan 5, 2016
84e2e12
FogBugz #348907-1: Fix A10 SyCon build error - remove child->parent s…
Jan 19, 2016
ac30598
FogBugz #348907-2: Update socfpga_defconfig to include A10 SyCon
Jan 19, 2016
f358632
FogBugz #338696: Update socfpga_defconfig for PCI-E reference design
thloh Dec 3, 2015
4d330c9
FogBugz #350137: Fix A10SyCon Button Export Crash
Jan 26, 2016
48c2934
FogBugz #353158: Stratix10 SWVP ethernet not working.
Jan 28, 2016
97e5ffc
FogBugz #352782: Fix A10SyCon Button Indexing
Jan 26, 2016
f96ce1c
FogBugz #352163: fix error checking in interrupt latency driver
Jan 25, 2016
c29507d
FogBugz #352163-2: fix error checking in interrupt latency driver
Feb 8, 2016
dfa694d
EDAC, altera: Do not build it as a module
Apr 17, 2015
88cc7c2
FogBugz #355420: Change of_gen_pool_get() to of_get_named_gen_pool()
Feb 10, 2016
f603a32
FogBugz #355420-2: dts: socfpga: Fix spidev WARN_ON() during boot.
Feb 9, 2016
45ae4d3
net/phy: micrel: Be more const correct
Patater Jun 5, 2015
77c17fa
net/phy: micrel: Comment MMD address of extended registers
Patater Jun 5, 2015
817f199
net/phy: micrel: Center FLP timing at 16ms
Patater Jun 5, 2015
fdbc8fc
mtd: nand: denali: max_banks calculation changed in revision 5.1
Jul 21, 2015
a812953
mtd: nand: denali: pass col argument to READID operation
ejoerns Sep 18, 2015
653f092
nios2: Remove unnecessary #ifdef guards
tklauser Nov 6, 2015
17f77e7
nios2: fix cache coherency
Nov 26, 2015
d224b53
ARM: socfpga: dts: add clock fields for I2C, UART and USB on Arria10
Sep 22, 2015
98f6fc0
clk: socfpga: allow for multiple parents on Arria10 periph clocks
Feb 22, 2016
d3e6c51
Revert "FogBugz #282531-1: Add "pwr-en" dts property to enable the PW…
Feb 23, 2016
783daad
Revert "FogBugz #282531-2: add pwr-en to the arria10 dts board file"
Feb 23, 2016
6b7c3c9
FogBugz #358974: remove 25MHz clock limit on Arria10 SD/MMC
Feb 23, 2016
7bb7340
FogBugz #354520: Stratix10 SWVP USB not working.
Feb 3, 2016
1861f57
FogBugz #355518: Stratix10 SWVP device tree needs updating.
Feb 3, 2016
8d095a2
arm64: config: Add Designware 8250 serial driver to
Feb 22, 2016
fcdf732
FogBugz #358574: SMP not functional on Stratix10 SWVP
Feb 22, 2016
5b6b146
configfs: Implement binary attributes (v4)
pantoniou Jun 12, 2014
a01d11a
OF: DT-Overlay configfs interface (v5)
pantoniou Dec 4, 2013
d098897
scripts/dtc: Update to Pantelis Antoniou's branch dt-overlays6
Feb 26, 2016
388b303
of/overlay: add of overlay notifications
Feb 11, 2016
d5b587b
fpga: add bindings document for fpga region
Jul 15, 2015
b91f456
ARM: socfpga: add bindings document for fpga bridge drivers
Jul 11, 2013
0e72a0c
add sysfs document for fpga bridge class
Oct 23, 2014
6f9157a
fpga: add fpga bridge framework
Oct 22, 2015
3427978
fpga: fpga-region: device tree control for FPGA
Jun 19, 2015
90741cf
ARM: socfpga: fpga bridge driver support
Jul 11, 2013
c2923d5
socfpga.dtsi: add base fpga region and fpga bridges
Feb 26, 2016
4629ad6
socfpga_defconfig: enable fpga overlay support
Feb 26, 2016
1224831
FogBugz #358986: qspi stack trace with 4.1-ltsi Linux kernel
Feb 29, 2016
4c6c1ec
ARM: socfpga: dts: Add missing clock and interrupt fields for Arria10…
Mar 8, 2016
983d349
ARM: DT: Enable symbols when CONFIG_OF_OVERLAY is used
pantoniou Dec 6, 2014
c816eac
PCI: altera: Fix altera_pcie_link_is_up()
Mar 2, 2016
451753c
stmmac: socfpga: remove extra call to socfpga_dwmac_setup
Apr 14, 2016
e8459f0
compiler-gcc: integrate the various compiler-gcc[345].h files
JoePerches Jun 25, 2015
cffe369
compiler-gcc: disable -ftracer for __noclone functions
bonzini Mar 31, 2016
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2 changes: 1 addition & 1 deletion Documentation/ABI/testing/configfs-usb-gadget-loopback
Original file line number Diff line number Diff line change
Expand Up @@ -5,4 +5,4 @@ Description:
The attributes:

qlen - depth of loopback queue
bulk_buflen - buffer length
buflen - buffer length
2 changes: 1 addition & 1 deletion Documentation/ABI/testing/configfs-usb-gadget-sourcesink
Original file line number Diff line number Diff line change
Expand Up @@ -9,4 +9,4 @@ Description:
isoc_maxpacket - 0 - 1023 (fs), 0 - 1024 (hs/ss)
isoc_mult - 0..2 (hs/ss only)
isoc_maxburst - 0..15 (ss only)
qlen - buffer length
buflen - buffer length
26 changes: 19 additions & 7 deletions Documentation/ABI/testing/ima_policy
Original file line number Diff line number Diff line change
Expand Up @@ -20,17 +20,19 @@ Description:
action: measure | dont_measure | appraise | dont_appraise | audit
condition:= base | lsm [option]
base: [[func=] [mask=] [fsmagic=] [fsuuid=] [uid=]
[fowner]]
[euid=] [fowner=]]
lsm: [[subj_user=] [subj_role=] [subj_type=]
[obj_user=] [obj_role=] [obj_type=]]
option: [[appraise_type=]] [permit_directio]

base: func:= [BPRM_CHECK][MMAP_CHECK][FILE_CHECK][MODULE_CHECK]
[FIRMWARE_CHECK]
mask:= [MAY_READ] [MAY_WRITE] [MAY_APPEND] [MAY_EXEC]
mask:= [[^]MAY_READ] [[^]MAY_WRITE] [[^]MAY_APPEND]
[[^]MAY_EXEC]
fsmagic:= hex value
fsuuid:= file system UUID (e.g 8bcbe394-4f13-4144-be8e-5aa9ea2ce2f6)
uid:= decimal value
euid:= decimal value
fowner:=decimal value
lsm: are LSM specific
option: appraise_type:= [imasig]
Expand All @@ -49,11 +51,25 @@ Description:
dont_measure fsmagic=0x01021994
dont_appraise fsmagic=0x01021994
# RAMFS_MAGIC
dont_measure fsmagic=0x858458f6
dont_appraise fsmagic=0x858458f6
# DEVPTS_SUPER_MAGIC
dont_measure fsmagic=0x1cd1
dont_appraise fsmagic=0x1cd1
# BINFMTFS_MAGIC
dont_measure fsmagic=0x42494e4d
dont_appraise fsmagic=0x42494e4d
# SECURITYFS_MAGIC
dont_measure fsmagic=0x73636673
dont_appraise fsmagic=0x73636673
# SELINUX_MAGIC
dont_measure fsmagic=0xf97cff8c
dont_appraise fsmagic=0xf97cff8c
# CGROUP_SUPER_MAGIC
dont_measure fsmagic=0x27e0eb
dont_appraise fsmagic=0x27e0eb
# NSFS_MAGIC
dont_measure fsmagic=0x6e736673
dont_appraise fsmagic=0x6e736673

measure func=BPRM_CHECK
measure func=FILE_MMAP mask=MAY_EXEC
Expand All @@ -70,10 +86,6 @@ Description:
Examples of LSM specific definitions:

SELinux:
# SELINUX_MAGIC
dont_measure fsmagic=0xf97cff8c
dont_appraise fsmagic=0xf97cff8c

dont_measure obj_type=var_log_t
dont_appraise obj_type=var_log_t
dont_measure obj_type=auditd_log_t
Expand Down
11 changes: 11 additions & 0 deletions Documentation/ABI/testing/sysfs-ata
Original file line number Diff line number Diff line change
Expand Up @@ -90,6 +90,17 @@ gscr
130: SATA_PMP_GSCR_SII_GPIO
Only valid if the device is a PM.

trim

Shows the DSM TRIM mode currently used by the device. Valid
values are:
unsupported: Drive does not support DSM TRIM
unqueued: Drive supports unqueued DSM TRIM only
queued: Drive supports queued DSM TRIM
forced_unqueued: Drive's unqueued DSM support is known to be
buggy and only unqueued TRIM commands
are sent

spdn_cnt

Number of time libata decided to lower the speed of link due to errors.
Expand Down
6 changes: 2 additions & 4 deletions Documentation/ABI/testing/sysfs-bus-iio
Original file line number Diff line number Diff line change
Expand Up @@ -1165,10 +1165,8 @@ Description:
object is near the sensor, usually be observing
reflectivity of infrared or ultrasound emitted.
Often these sensors are unit less and as such conversion
to SI units is not possible. Where it is, the units should
be meters. If such a conversion is not possible, the reported
values should behave in the same way as a distance, i.e. lower
values indicate something is closer to the sensor.
to SI units is not possible. Higher proximity measurements
indicate closer objects, and vice versa.

What: /sys/.../iio:deviceX/in_illuminance_input
What: /sys/.../iio:deviceX/in_illuminance_raw
Expand Down
11 changes: 11 additions & 0 deletions Documentation/ABI/testing/sysfs-class-fpga-bridge
Original file line number Diff line number Diff line change
@@ -0,0 +1,11 @@
What: /sys/class/fpga_bridge/<bridge>/name
Date: January 2016
KernelVersion: 4.5
Contact: Alan Tull <atull@opensource.altera.com>
Description: Name of low level FPGA bridge driver.

What: /sys/class/fpga_bridge/<bridge>/state
Date: January 2016
KernelVersion: 4.5
Contact: Alan Tull <atull@opensource.altera.com>
Description: Show bridge state as "enabled" or "disabled"
37 changes: 37 additions & 0 deletions Documentation/ABI/testing/sysfs-class-fpga-manager
Original file line number Diff line number Diff line change
@@ -0,0 +1,37 @@
What: /sys/class/fpga_manager/<fpga>/name
Date: August 2015
KernelVersion: 4.3
Contact: Alan Tull <atull@opensource.altera.com>
Description: Name of low level fpga manager driver.

What: /sys/class/fpga_manager/<fpga>/state
Date: August 2015
KernelVersion: 4.3
Contact: Alan Tull <atull@opensource.altera.com>
Description: Read fpga manager state as a string.
The intent is to provide enough detail that if something goes
wrong during FPGA programming (something that the driver can't
fix) then userspace can know, i.e. if the firmware request
fails, that could be due to not being able to find the firmware
file.

This is a superset of FPGA states and fpga manager driver
states. The fpga manager driver is walking through these steps
to get the FPGA into a known operating state. It's a sequence,
though some steps may get skipped. Valid FPGA states will vary
by manufacturer; this is a superset.

* unknown = can't determine state
* power off = FPGA power is off
* power up = FPGA reports power is up
* reset = FPGA held in reset state
* firmware request = firmware class request in progress
* firmware request error = firmware request failed
* write init = preparing FPGA for programming
* write init error = Error while preparing FPGA for
programming
* write = FPGA ready to receive image data
* write error = Error while programming
* write complete = Doing post programming steps
* write complete error = Error while doing post programming
* operating = FPGA is programmed and operating
29 changes: 17 additions & 12 deletions Documentation/DMA-API-HOWTO.txt
Original file line number Diff line number Diff line change
Expand Up @@ -25,13 +25,18 @@ physical addresses. These are the addresses in /proc/iomem. The physical
address is not directly useful to a driver; it must use ioremap() to map
the space and produce a virtual address.

I/O devices use a third kind of address: a "bus address" or "DMA address".
If a device has registers at an MMIO address, or if it performs DMA to read
or write system memory, the addresses used by the device are bus addresses.
In some systems, bus addresses are identical to CPU physical addresses, but
in general they are not. IOMMUs and host bridges can produce arbitrary
I/O devices use a third kind of address: a "bus address". If a device has
registers at an MMIO address, or if it performs DMA to read or write system
memory, the addresses used by the device are bus addresses. In some
systems, bus addresses are identical to CPU physical addresses, but in
general they are not. IOMMUs and host bridges can produce arbitrary
mappings between physical and bus addresses.

From a device's point of view, DMA uses the bus address space, but it may
be restricted to a subset of that space. For example, even if a system
supports 64-bit addresses for main memory and PCI BARs, it may use an IOMMU
so devices only need to use 32-bit DMA addresses.

Here's a picture and some examples:

CPU CPU Bus
Expand Down Expand Up @@ -72,11 +77,11 @@ can use virtual address X to access the buffer, but the device itself
cannot because DMA doesn't go through the CPU virtual memory system.

In some simple systems, the device can do DMA directly to physical address
Y. But in many others, there is IOMMU hardware that translates bus
Y. But in many others, there is IOMMU hardware that translates DMA
addresses to physical addresses, e.g., it translates Z to Y. This is part
of the reason for the DMA API: the driver can give a virtual address X to
an interface like dma_map_single(), which sets up any required IOMMU
mapping and returns the bus address Z. The driver then tells the device to
mapping and returns the DMA address Z. The driver then tells the device to
do DMA to Z, and the IOMMU maps it to the buffer at address Y in system
RAM.

Expand All @@ -98,7 +103,7 @@ First of all, you should make sure
#include <linux/dma-mapping.h>

is in your driver, which provides the definition of dma_addr_t. This type
can hold any valid DMA or bus address for the platform and should be used
can hold any valid DMA address for the platform and should be used
everywhere you hold a DMA address returned from the DMA mapping functions.

What memory is DMA'able?
Expand Down Expand Up @@ -316,7 +321,7 @@ There are two types of DMA mappings:
Think of "consistent" as "synchronous" or "coherent".

The current default is to return consistent memory in the low 32
bits of the bus space. However, for future compatibility you should
bits of the DMA space. However, for future compatibility you should
set the consistent mask even if this default is fine for your
driver.

Expand Down Expand Up @@ -403,7 +408,7 @@ dma_alloc_coherent() returns two values: the virtual address which you
can use to access it from the CPU and dma_handle which you pass to the
card.

The CPU virtual address and the DMA bus address are both
The CPU virtual address and the DMA address are both
guaranteed to be aligned to the smallest PAGE_SIZE order which
is greater than or equal to the requested size. This invariant
exists (for example) to guarantee that if you allocate a chunk
Expand Down Expand Up @@ -645,8 +650,8 @@ PLEASE NOTE: The 'nents' argument to the dma_unmap_sg call must be
dma_map_sg call.

Every dma_map_{single,sg}() call should have its dma_unmap_{single,sg}()
counterpart, because the bus address space is a shared resource and
you could render the machine unusable by consuming all bus addresses.
counterpart, because the DMA address space is a shared resource and
you could render the machine unusable by consuming all DMA addresses.

If you need to use the same streaming DMA region multiple times and touch
the data in between the DMA transfers, the buffer needs to be synced
Expand Down
30 changes: 15 additions & 15 deletions Documentation/DMA-API.txt
Original file line number Diff line number Diff line change
Expand Up @@ -18,10 +18,10 @@ Part I - dma_ API
To get the dma_ API, you must #include <linux/dma-mapping.h>. This
provides dma_addr_t and the interfaces described below.

A dma_addr_t can hold any valid DMA or bus address for the platform. It
can be given to a device to use as a DMA source or target. A CPU cannot
reference a dma_addr_t directly because there may be translation between
its physical address space and the bus address space.
A dma_addr_t can hold any valid DMA address for the platform. It can be
given to a device to use as a DMA source or target. A CPU cannot reference
a dma_addr_t directly because there may be translation between its physical
address space and the DMA address space.

Part Ia - Using large DMA-coherent buffers
------------------------------------------
Expand All @@ -42,7 +42,7 @@ It returns a pointer to the allocated region (in the processor's virtual
address space) or NULL if the allocation failed.

It also returns a <dma_handle> which may be cast to an unsigned integer the
same width as the bus and given to the device as the bus address base of
same width as the bus and given to the device as the DMA address base of
the region.

Note: consistent memory can be expensive on some platforms, and the
Expand Down Expand Up @@ -193,7 +193,7 @@ dma_map_single(struct device *dev, void *cpu_addr, size_t size,
enum dma_data_direction direction)

Maps a piece of processor virtual memory so it can be accessed by the
device and returns the bus address of the memory.
device and returns the DMA address of the memory.

The direction for both APIs may be converted freely by casting.
However the dma_ API uses a strongly typed enumerator for its
Expand All @@ -212,20 +212,20 @@ contiguous piece of memory. For this reason, memory to be mapped by
this API should be obtained from sources which guarantee it to be
physically contiguous (like kmalloc).

Further, the bus address of the memory must be within the
Further, the DMA address of the memory must be within the
dma_mask of the device (the dma_mask is a bit mask of the
addressable region for the device, i.e., if the bus address of
the memory ANDed with the dma_mask is still equal to the bus
addressable region for the device, i.e., if the DMA address of
the memory ANDed with the dma_mask is still equal to the DMA
address, then the device can perform DMA to the memory). To
ensure that the memory allocated by kmalloc is within the dma_mask,
the driver may specify various platform-dependent flags to restrict
the bus address range of the allocation (e.g., on x86, GFP_DMA
guarantees to be within the first 16MB of available bus addresses,
the DMA address range of the allocation (e.g., on x86, GFP_DMA
guarantees to be within the first 16MB of available DMA addresses,
as required by ISA devices).

Note also that the above constraints on physical contiguity and
dma_mask may not apply if the platform has an IOMMU (a device which
maps an I/O bus address to a physical memory address). However, to be
maps an I/O DMA address to a physical memory address). However, to be
portable, device driver writers may *not* assume that such an IOMMU
exists.

Expand Down Expand Up @@ -296,7 +296,7 @@ reduce current DMA mapping usage or delay and try again later).
dma_map_sg(struct device *dev, struct scatterlist *sg,
int nents, enum dma_data_direction direction)

Returns: the number of bus address segments mapped (this may be shorter
Returns: the number of DMA address segments mapped (this may be shorter
than <nents> passed in if some elements of the scatter/gather list are
physically or virtually adjacent and an IOMMU maps them with a single
entry).
Expand Down Expand Up @@ -340,7 +340,7 @@ must be the same as those and passed in to the scatter/gather mapping
API.

Note: <nents> must be the number you passed in, *not* the number of
bus address entries returned.
DMA address entries returned.

void
dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle, size_t size,
Expand Down Expand Up @@ -507,7 +507,7 @@ it's asked for coherent memory for this device.
phys_addr is the CPU physical address to which the memory is currently
assigned (this will be ioremapped so the CPU can access the region).

device_addr is the bus address the device needs to be programmed
device_addr is the DMA address the device needs to be programmed
with to actually address this memory (this will be handed out as the
dma_addr_t in dma_alloc_coherent()).

Expand Down
28 changes: 14 additions & 14 deletions Documentation/HOWTO
Original file line number Diff line number Diff line change
Expand Up @@ -218,16 +218,16 @@ The development process
Linux kernel development process currently consists of a few different
main kernel "branches" and lots of different subsystem-specific kernel
branches. These different branches are:
- main 3.x kernel tree
- 3.x.y -stable kernel tree
- 3.x -git kernel patches
- main 4.x kernel tree
- 4.x.y -stable kernel tree
- 4.x -git kernel patches
- subsystem specific kernel trees and patches
- the 3.x -next kernel tree for integration tests
- the 4.x -next kernel tree for integration tests

3.x kernel tree
4.x kernel tree
-----------------
3.x kernels are maintained by Linus Torvalds, and can be found on
kernel.org in the pub/linux/kernel/v3.x/ directory. Its development
4.x kernels are maintained by Linus Torvalds, and can be found on
kernel.org in the pub/linux/kernel/v4.x/ directory. Its development
process is as follows:
- As soon as a new kernel is released a two weeks window is open,
during this period of time maintainers can submit big diffs to
Expand Down Expand Up @@ -262,20 +262,20 @@ mailing list about kernel releases:
released according to perceived bug status, not according to a
preconceived timeline."

3.x.y -stable kernel tree
4.x.y -stable kernel tree
---------------------------
Kernels with 3-part versions are -stable kernels. They contain
relatively small and critical fixes for security problems or significant
regressions discovered in a given 3.x kernel.
regressions discovered in a given 4.x kernel.

This is the recommended branch for users who want the most recent stable
kernel and are not interested in helping test development/experimental
versions.

If no 3.x.y kernel is available, then the highest numbered 3.x
If no 4.x.y kernel is available, then the highest numbered 4.x
kernel is the current stable kernel.

3.x.y are maintained by the "stable" team <stable@vger.kernel.org>, and
4.x.y are maintained by the "stable" team <stable@vger.kernel.org>, and
are released as needs dictate. The normal release period is approximately
two weeks, but it can be longer if there are no pressing problems. A
security-related problem, instead, can cause a release to happen almost
Expand All @@ -285,7 +285,7 @@ The file Documentation/stable_kernel_rules.txt in the kernel tree
documents what kinds of changes are acceptable for the -stable tree, and
how the release process works.

3.x -git patches
4.x -git patches
------------------
These are daily snapshots of Linus' kernel tree which are managed in a
git repository (hence the name.) These patches are usually released
Expand Down Expand Up @@ -317,9 +317,9 @@ revisions to it, and maintainers can mark patches as under review,
accepted, or rejected. Most of these patchwork sites are listed at
http://patchwork.kernel.org/.

3.x -next kernel tree for integration tests
4.x -next kernel tree for integration tests
---------------------------------------------
Before updates from subsystem trees are merged into the mainline 3.x
Before updates from subsystem trees are merged into the mainline 4.x
tree, they need to be integration-tested. For this purpose, a special
testing repository exists into which virtually all subsystem trees are
pulled on an almost daily basis:
Expand Down
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