Clean up sink pause handling

Signed-off-by: Alex Forencich <alex@alexforencich.com>
alexforencich · Aug 13, 2023 · 1d05540 · 1d05540
1 parent ac7450e
commit 1d05540
Showing 1 changed file with 5 additions and 3 deletions.
diff --git a/cocotbext/pcie/xilinx/us/interface.py b/cocotbext/pcie/xilinx/us/interface.py
@@ -436,7 +436,7 @@ async def _run_sink(self):
         wake_event = self.wake_event.wait()
 
         while True:
-            pause_sample = self.pause
+            pause_sample = bool(self.pause)
 
             await clock_edge_event
 
@@ -453,9 +453,11 @@ async def _run_sink(self):
                 self.bus.sample(self.sample_obj)
                 self.sample_sync.set()
 
-            self.bus.tready.value = (not self.full() and not pause_sample)
+            paused = self.full() or pause_sample
 
-            if not tvalid_sample or (self.pause and pause_sample) or self.full():
+            self.bus.tready.value = not paused
+
+            if (not tvalid_sample or paused) and (pause_sample == bool(self.pause)):
                 self.wake_event.clear()
                 await wake_event