Name		Name	Last commit message	Last commit date
Latest commit History 3 Commits
Add basic		Add basic
New folder (2)		New folder (2)
New folder (3)		New folder (3)
New folder		New folder
OoO		OoO
comb_shifter		comb_shifter
combine_add_datapath		combine_add_datapath
combine_rg_file_inst_mem_shifter		combine_rg_file_inst_mem_shifter
cpsr		cpsr
data_memory		data_memory
final_datapath_with_forwarding		final_datapath_with_forwarding
forwarding		forwarding
inst_mem		inst_mem
modelsim folder/examples		modelsim folder/examples
mux_2x1_32bit		mux_2x1_32bit
mux_structural		mux_structural
new reg_file		new reg_file
new_data_mem		new_data_mem
new_rotater		new_rotater
new_unpipelined		new_unpipelined
pc_incrementer		pc_incrementer
reg_file_inst_mem_combine_module		reg_file_inst_mem_combine_module
register		register
shift_rotate		shift_rotate
work		work
ALU.v		ALU.v
ALU.v.bak		ALU.v.bak
ALU_tb.v		ALU_tb.v
ALU_tb.v.bak		ALU_tb.v.bak
Arithematic logic unit.cr.mti		Arithematic logic unit.cr.mti
Arithematic logic unit.mpf		Arithematic logic unit.mpf
README.md		README.md
and_tb.v		and_tb.v
and_tb.v.bak		and_tb.v.bak
instruction_memory.v		instruction_memory.v
instruction_memory.v.bak		instruction_memory.v.bak
pc_incrementer.v		pc_incrementer.v
pc_incrementer.v.bak		pc_incrementer.v.bak
top.v		top.v
top.v.bak		top.v.bak
trial.cr.mti		trial.cr.mti
trial.mpf		trial.mpf
vish_stacktrace.vstf		vish_stacktrace.vstf
vsim.wlf		vsim.wlf