Pinned Loading
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Ito
Ito PublicMulti-branch trading-system engineering foundation for deterministic simulation, risk controls, venue connectivity, FPGA-oriented gating, and production-readiness validation
Python
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Kestrel
Kestrel Public140M+ msg/sec zero-copy NASDAQ ITCH 5.0 LOB engine in C++20 / SIMD, SystemVerilog AXI4-Stream FPGA core, and Linux PCIe DMA driver
C++
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Zerene
Zerene PublicInstitutional market microstructure simulator built for quants tired of 'Sharpe 4.2' pandas backtesters crying when an HFT front-runs them in 400μs
Python
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ORX-1
ORX-1 PublicOpen SystemVerilog edge-AI SoC reference design with an RV32I control core, deterministic sensor pipeline, INT8 neural accelerator, secure boot, formal interface checks, and energy-proxy monitoring
SystemVerilog
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Klint-32M
Klint-32M PublicOpen research architecture for generative financial time-series modeling
Jupyter Notebook
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