🔒 MLSS — Multi-Layer Security System Simulator

Intel 8086 Real-Mode Assembly · EMU8086 · Computer Organization & Assembly Language Project

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📌 Project Overview

MLSS (Multi-Layer Security System) is a comprehensive four-layer authentication controller simulator written entirely in Intel 8086 real-mode assembly. It models an embedded access-control security micro-controller operating directly on bare metal without an operating system.

The project demonstrates full-stack x86 low-level system programming:

• Direct Hardware Interfacing: Hardware I/O control for the 8253 Programmable Interval Timer (PIT), 8259 Programmable Interrupt Controller (PIC), and 8255 Programmable Peripheral Interface (PPI).
• Custom Interrupt Handling: Runtime patching of the Interrupt Vector Table (IVT) to handle system timer ticks (INT 08h) and keyboard hardware scan-codes (INT 09h).
• Security & Data Structures: Circular ring-buffer logging, index-salted XOR password hashing, Linear Congruential Generator (LCG) OTP generation, and Kernighan bit-counting algorithm for biometric Hamming-distance matching.
• Text-Mode GUI Engine: Custom VGA text-mode UI engine with progress bars, status overlays, animated biometric scanning, and border rendering drawn through BIOS INT 10h calls.
• Asynchronous Watchdog & Alarm Subsystem: Hardware-driven timer interrupt handling for security timeouts and alarm states.

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⚙️ Architecture & Hardware Matrix

Hardware Concept	Micro-Chip / Mechanism	Assembly Implementation	Location
Interval Timing	8253 PIT (Channel 0 read for OTP seeding, tick driving)	Dynamic timer tick handling & watchdog countdown	isr_timer.asm, layer2_otp.asm
Interrupt Controller	8259 PIC	OCW2 End-of-Interrupt (EOI) signals issued after ISR execution	main.asm, isr_timer.asm
Peripheral Controller	8255 PPI (Ports A/B/C)	Hardware control port writes during door unlock sequences	layer4_admin.asm
IVT Vector Patching	IVT modification (0000:0020h & 0000:0024h)	Dynamic runtime installation of INT 08h & INT 09h ISRs	main.asm
Video Rendering	VGA Text Mode (80×25)	BIOS INT 10h cursor manipulation & attribute drawing	ui_engine.asm, debug_overlay.asm
Ring Buffer	256-Byte Circular Event Log	Modulo-256 head pointer wrapping	data_segment.asm, isr_keyboard.asm
XOR PIN Hash	hash[i] = pin[i] ⊕ (i × 5Ah)	Salted index-based XOR password hashing	layer1_pin.asm
Pseudorandom OTP	seed = (seed × 214Dh + 2053h) mod 65536	LCG-based random number generation	layer2_otp.asm
Biometric Alignment	Kernighan Bit-Clear Algorithm	Hamming distance bit-mask comparison	layer3_bio.asm

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🔑 4-Layer Security Authentication Pipeline

┌─────────────────┐    ┌──────────────────┐    ┌──────────────────┐    ┌──────────────────┐
│ Layer 1: PIN    │───>│ Layer 2: OTP     │───>│ Layer 3: Bio     │───>│ Layer 4: Admin   │
│ XOR Hash Check  │    │ LCG + PIT Watchdog│   │ Hamming Distance │    │ PPI Hardware I/O │
└─────────────────┘    └──────────────────┘    └──────────────────┘    └──────────────────┘

1. Layer 1 — PIN Entry & XOR Hash Verification:

   • 4-digit secret PIN entry masked on screen as ****.
   • Evaluated against pre-hashed store using index-salted XOR transformation (DO_PIN_HASH).
   • Locks system after 3 consecutive failures.

2. Layer 2 — One-Time Password (OTP) & Watchdog Countdown:

   • Generates a dynamic 6-digit OTP using an LCG seeded by hardware timer ticks.
   • Enforces a live progress bar watchdog countdown driven asynchronously via INT 08h.

3. Layer 3 — Biometric Scan Simulation:

   • Renders a 64-byte fingerprint scan matrix animation.
   • Computes bitwise difference against stored template (FP_TEMPLATE) using Kernighan's bit-counting method.

4. Layer 4 — Privileged Admin Console:

   • Gated strictly by flag condition (FLAG_AUTH_L1 | FLAG_AUTH_L2 | FLAG_AUTH_L3).
   • Features 5 admin actions: System Event Log Review, PIN Re-configuration, Hardware Door Actuation (via 8255 PPI), Alarm Override, and System Reboot.

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📂 Project Structure

mlss/
├── mlss.asm              # Primary build entry file (includes all modules in order)
├── constants.asm         # EQU port mappings (PIT/PIC/8255), flag bitmasks, and limits
├── data_segment.asm      # Unified DATA segment: PIN hash, OTP, log buffer, UI text
├── ui_engine.asm         # VGA text-mode graphics: borders, progress bar, header/footer
├── isr_timer.asm         # Hardware INT 08h ISR: watchdog decrement, EOI handling
├── isr_keyboard.asm      # Hardware INT 09h ISR: 16-byte scan-code ring buffer decoder
├── layer1_pin.asm        # Security Layer 1: 4-digit PIN hash matching
├── layer2_otp.asm        # Security Layer 2: Timer-seeded LCG OTP generator
├── layer3_bio.asm        # Security Layer 3: Hamming distance biometric match
├── layer4_admin.asm      # Security Layer 4: Administrative control console
├── main.asm              # System bootstrap: segment setup, IVT patching, startup
├── test_mlss.asm         # Automated test suite (6 integrated verification tests)
├── debug_overlay.asm     # Real-time register, stack & watchdog diagnostic overlay
└── MLSS_Code_Review.md   # Architectural documentation & code review notes

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🛠️ Build & Run Instructions (EMU8086)

1. Download & Launch EMU8086: Install EMU8086 (v4.x recommended).
2. Open Master File: Launch EMU8086, select File → Open, and open mlss.asm. Ensure all module files are in the same directory.
3. Assemble: Click Emulate (or press F5).
4. Execution & Debugging:
   • Press F9 to run the complete simulation at full speed.
   • Press F8 to single-step instructions (ideal for tracing ISR execution).
   • Toggle diagnostic overlay via DEBUG_MODE EQU 1 in debug_overlay.asm.

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🧪 Demo Credentials

Module	Default Input	Behaviour
Layer 1	1234	Matches pre-computed XOR hash (PIN_HASH).
Layer 2	Dynamic (On-Screen)	Generated live from 8253 PIT seed; type within time limit.
Layer 3	Any Keypress	Generates fingerprint matrix and validates Hamming score.
Layer 4	Automated	Unlocks admin menu upon completing Layers 1–3.

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📜 License & Credits

Developed as part of the Computer Organization & Assembly Language (COAL) course. Built using pure 8086 real-mode assembly for EMU8086.