Add riscv sequential mode detection ## Summary - recognize riscv64 explicitly in mipp.h; - make riscv64 resolve to the existing sequential no-intrinsics mode instead of leaking host SIMD backends.

[carlosqwqqwq]

Why

MIPP already has a sequential fallback mode for unsupported architectures, which is the right conservative baseline for riscv64 until a dedicated backend exists. However, the current architecture detection still derives backend selection directly from host SIMD builtins such as __SSE__, __AVX__, __AVX512F__, __ARM_NEON, and __ARM_FEATURE_SVE. During forced-target or cross-target validation, those host macros can leak into preprocessing and make a riscv64 portability check incorrectly select x86 or ARM SIMD paths.

What changed

• Add explicit MIPP_RISCV and MIPP_RISCV64 target markers in include/mipp.h.
• Clear host x86 and ARM SIMD builtins when the target is forced to __riscv, so riscv64 portability checks do not inherit host SIMD state.
• Let __riscv fall through to MIPP's existing sequential implementation path instead of matching x86 or ARM backends.
• Expose InstructionType / InstructionFullType as RISC-V_NO_INTRINSICS or RISC-V64_NO_INTRINSICS when the library is compiled for RISC-V sequential mode.
• Update README.md to document that the current RISC-V path uses MIPP's existing sequential mode until a dedicated backend is added.

Verification

• Ran the native CMake/Ninja test build successfully:
  • cmake -S . -B build-native -G Ninja -DMIPP_EXAMPLES_EXE=OFF -DMIPP_STATIC_LIB=OFF -DMIPP_ENABLE_BACKTRACE=OFF
  • cmake --build build-native --parallel 4
  • ctest --test-dir build-native --output-on-failure
• Confirmed the default native test suite passes in the existing host SIMD configuration.
• Preprocessed mipp.h with -D__riscv=1 -D__riscv_xlen=64 and confirmed it reports MIPP_RISCV, MIPP_RISCV64, MIPP_NO_INTRINSICS, MIPP_NO, MIPP_REGISTER_SIZE=0, and MIPP_REQUIRED_ALIGNMENT=1, without enabling MIPP_SSE, MIPP_AVX, MIPP_AVX512, or MIPP_NEON.
• Compiled a forced-riscv64 smoke translation unit that includes mipp.h, verifies no x86 or ARM backend macros leak into the target, and checks that RegisterSizeBit == 0 and RequiredAlignment == 1.
• Ran the sequential fallback test build in forced riscv64 mode successfully:
  • cmake -S . -B build-riscv-seq -G Ninja -DMIPP_EXAMPLES_EXE=OFF -DMIPP_STATIC_LIB=OFF -DMIPP_ENABLE_BACKTRACE=OFF -DMIPP_NO_INTRINSICS=ON -DCMAKE_CXX_FLAGS='-D__riscv=1 -D__riscv_xlen=64'
  • cmake --build build-riscv-seq --parallel 4
  • ctest --test-dir build-riscv-seq --output-on-failure
• Verified real riscv64 cross-compilation and execution in Docker (ubuntu:24.04):
  • built examples/operator.cpp natively and with riscv64-linux-gnu-g++;
  • confirmed the riscv64 binary is ELF64 / Machine: RISC-V via file and readelf -h;
  • ran the riscv64 example successfully with qemu-riscv64-static -L /usr/riscv64-linux-gnu;
  • confirmed the runtime output reports Instr. type: RISC-V, Reg. size: 0 bits, and Reg. lanes: 1, matching the intended sequential fallback.

Notes

This is a conservative portability patch. It does not add RVV or any other dedicated RISC-V SIMD backend. The goal is to make riscv64 resolve to MIPP's existing sequential mode correctly and to stop host SIMD assumptions from leaking into cross-target validation.