Configurable Traffic Light Controller (Verilog)

A synthesizable, configurable traffic light controller implemented in Verilog HDL.

Features

• Two-way intersection (NS / EW)
• Moore FSM with synchronous reset
• Parameterized 1-second timebase
• Programmable green and yellow durations
• Clean separation of control, timing, and top-level wiring

Architecture

• traffic_light_controller.v: FSM, timer, output decode
• timebase_1s.v: 1-second tick generator (clock-agnostic)
• top_module.v: system integration

Verification

• Independent testbenches for:
  • Timebase
  • Traffic controller
  • Full system
• Waveforms included in sim/waveforms

Tools

• Vivado (xsim)
• Verilog HDL

Notes

This design avoids gated clocks and uses a clean enable-based timing model. It is intended for educational purposes and can be adapted for real-world applications with additional features like pedestrian signals or emergency vehicle preemption.

Design Notes

For a detailed explanation of the architecture, design decisions, timing strategy, FSM structure, and verification approach, see docs/design_notes.md.

This document contains the complete technical rationale behind the project and is recommended reading for anyone looking to fully understand the design.

Documentation

• FSM state diagram: docs/fsm_state_diagram.png
• Architecture overview: docs/architecture_block_diagram.png
• RTL schematic (Vivado): docs/Traffic_Light_Controller_Schematics.png
• Detailed design rationale: docs/design_notes.md