Add Register Spill to GC for all target processor architectures

[eightycc]

It is possible, as demonstrated by #10298, for a live memory pointer to exist only in a register when gc_collect is called. ports/espressif/mphalport.c:cpu_get_regs_and_sp() implements register spill for Xtensa processors. Similar spilling needs to be implemented, in a processor-dependent fashion, for other target processor architectures.

[tannewt]

I don't think RISC-V needs spilling because it doesn't have register windows. Instead, we'll want to copy out of the RISC-V registers.

[eightycc]

I don't think RISC-V needs spilling because it doesn't have register windows. Instead, we'll want to copy out of the RISC-V registers.

I think we mean the same thing. I was using the term spill in its more general sense, meaning to move register contents to RAM.