Regenerate using svd2rust 0.30.2

.github/workflows/check.yml

@@ -9,12 +9,12 @@ jobs:
     strategy:
       matrix:
         mcu: [bcm2835, bcm2837, bcm2711]
-        rust-version: [1.61.0, 1.62.1, 1.63.0, 1.64.0, 1.65.0, 1.66.1, 1.67.1, 1.68.0]
+        rust-version: [1.65.0, 1.66.1, 1.67.1, 1.68.2, 1.69.0, 1.70.0, 1.71.1, 1.72.1, 1.73.0]
 
     runs-on: ubuntu-latest
 
     steps:
-      - uses: actions/checkout@v3
+      - uses: actions/checkout@v4
 
       - name: Install Rust
         run: rustup default ${{ matrix.rust-version }}

crates/bcm2711-lpa/Cargo.toml

@@ -1,9 +1,9 @@
 [package]
 name = "bcm2711-lpa"
-version = "0.1.0"
+version = "0.2.0"
 authors = ["Po-Yi Tsai <abt8601@protonmail.ch>"]
 edition = "2021"
-rust-version = "1.61.0"
+rust-version = "1.65.0"
 description = "Peripheral access crate for BCM2711 found in the Raspberry Pi 4."
 repository = "https://github.com/abt8601/raspi-pacs"
 license = "Unlicense"

crates/bcm2711-lpa/src/aux.rs

@@ -1,16 +1,19 @@
 #[doc = r"Register block"]
 #[repr(C)]
+#[derive(Debug)]
 pub struct RegisterBlock {
     #[doc = "0x00 - Interrupt status"]
     pub irq: IRQ,
     #[doc = "0x04 - Enable sub-peripherals"]
     pub enables: ENABLES,
 }
-#[doc = "IRQ (rw) register accessor: an alias for `Reg<IRQ_SPEC>`"]
+#[doc = "IRQ (rw) register accessor: Interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq`]
+module"]
 pub type IRQ = crate::Reg<irq::IRQ_SPEC>;
 #[doc = "Interrupt status"]
 pub mod irq;
-#[doc = "ENABLES (rw) register accessor: an alias for `Reg<ENABLES_SPEC>`"]
+#[doc = "ENABLES (rw) register accessor: Enable sub-peripherals\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enables::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enables::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enables`]
+module"]
 pub type ENABLES = crate::Reg<enables::ENABLES_SPEC>;
 #[doc = "Enable sub-peripherals"]
 pub mod enables;

crates/bcm2711-lpa/src/aux/enables.rs

@@ -1,51 +1,19 @@
 #[doc = "Register `ENABLES` reader"]
-pub struct R(crate::R<ENABLES_SPEC>);
-impl core::ops::Deref for R {
-    type Target = crate::R<ENABLES_SPEC>;
-    #[inline(always)]
-    fn deref(&self) -> &Self::Target {
-        &self.0
-    }
-}
-impl From<crate::R<ENABLES_SPEC>> for R {
-    #[inline(always)]
-    fn from(reader: crate::R<ENABLES_SPEC>) -> Self {
-        R(reader)
-    }
-}
+pub type R = crate::R<ENABLES_SPEC>;
 #[doc = "Register `ENABLES` writer"]
-pub struct W(crate::W<ENABLES_SPEC>);
-impl core::ops::Deref for W {
-    type Target = crate::W<ENABLES_SPEC>;
-    #[inline(always)]
-    fn deref(&self) -> &Self::Target {
-        &self.0
-    }
-}
-impl core::ops::DerefMut for W {
-    #[inline(always)]
-    fn deref_mut(&mut self) -> &mut Self::Target {
-        &mut self.0
-    }
-}
-impl From<crate::W<ENABLES_SPEC>> for W {
-    #[inline(always)]
-    fn from(writer: crate::W<ENABLES_SPEC>) -> Self {
-        W(writer)
-    }
-}
+pub type W = crate::W<ENABLES_SPEC>;
 #[doc = "Field `UART_1` reader - UART1 enabled"]
-pub type UART_1_R = crate::BitReader<bool>;
+pub type UART_1_R = crate::BitReader;
 #[doc = "Field `UART_1` writer - UART1 enabled"]
-pub type UART_1_W<'a, const O: u8> = crate::BitWriter<'a, u32, ENABLES_SPEC, bool, O>;
+pub type UART_1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>;
 #[doc = "Field `SPI_1` reader - SPI1 enabled"]
-pub type SPI_1_R = crate::BitReader<bool>;
+pub type SPI_1_R = crate::BitReader;
 #[doc = "Field `SPI_1` writer - SPI1 enabled"]
-pub type SPI_1_W<'a, const O: u8> = crate::BitWriter<'a, u32, ENABLES_SPEC, bool, O>;
+pub type SPI_1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>;
 #[doc = "Field `SPI_2` reader - SPI2 enabled"]
-pub type SPI_2_R = crate::BitReader<bool>;
+pub type SPI_2_R = crate::BitReader;
 #[doc = "Field `SPI_2` writer - SPI2 enabled"]
-pub type SPI_2_W<'a, const O: u8> = crate::BitWriter<'a, u32, ENABLES_SPEC, bool, O>;
+pub type SPI_2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>;
 impl R {
     #[doc = "Bit 0 - UART1 enabled"]
     #[inline(always)]
@@ -63,44 +31,59 @@ impl R {
         SPI_2_R::new(((self.bits >> 2) & 1) != 0)
     }
 }
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("ENABLES")
+            .field("spi_2", &format_args!("{}", self.spi_2().bit()))
+            .field("spi_1", &format_args!("{}", self.spi_1().bit()))
+            .field("uart_1", &format_args!("{}", self.uart_1().bit()))
+            .finish()
+    }
+}
+impl core::fmt::Debug for crate::generic::Reg<ENABLES_SPEC> {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        self.read().fmt(f)
+    }
+}
 impl W {
     #[doc = "Bit 0 - UART1 enabled"]
     #[inline(always)]
     #[must_use]
-    pub fn uart_1(&mut self) -> UART_1_W<0> {
+    pub fn uart_1(&mut self) -> UART_1_W<ENABLES_SPEC, 0> {
         UART_1_W::new(self)
     }
     #[doc = "Bit 1 - SPI1 enabled"]
     #[inline(always)]
     #[must_use]
-    pub fn spi_1(&mut self) -> SPI_1_W<1> {
+    pub fn spi_1(&mut self) -> SPI_1_W<ENABLES_SPEC, 1> {
         SPI_1_W::new(self)
     }
     #[doc = "Bit 2 - SPI2 enabled"]
     #[inline(always)]
     #[must_use]
-    pub fn spi_2(&mut self) -> SPI_2_W<2> {
+    pub fn spi_2(&mut self) -> SPI_2_W<ENABLES_SPEC, 2> {
         SPI_2_W::new(self)
     }
-    #[doc = "Writes raw bits to the register."]
+    #[doc = r" Writes raw bits to the register."]
+    #[doc = r""]
+    #[doc = r" # Safety"]
+    #[doc = r""]
+    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
     #[inline(always)]
     pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
-        self.0.bits(bits);
+        self.bits = bits;
         self
     }
 }
-#[doc = "Enable sub-peripherals\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [enables](index.html) module"]
+#[doc = "Enable sub-peripherals\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enables::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enables::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct ENABLES_SPEC;
 impl crate::RegisterSpec for ENABLES_SPEC {
     type Ux = u32;
 }
-#[doc = "`read()` method returns [enables::R](R) reader structure"]
-impl crate::Readable for ENABLES_SPEC {
-    type Reader = R;
-}
-#[doc = "`write(|w| ..)` method takes [enables::W](W) writer structure"]
+#[doc = "`read()` method returns [`enables::R`](R) reader structure"]
+impl crate::Readable for ENABLES_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`enables::W`](W) writer structure"]
 impl crate::Writable for ENABLES_SPEC {
-    type Writer = W;
     const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
     const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
 }

crates/bcm2711-lpa/src/aux/irq.rs

@@ -1,51 +1,19 @@
 #[doc = "Register `IRQ` reader"]
-pub struct R(crate::R<IRQ_SPEC>);
-impl core::ops::Deref for R {
-    type Target = crate::R<IRQ_SPEC>;
-    #[inline(always)]
-    fn deref(&self) -> &Self::Target {
-        &self.0
-    }
-}
-impl From<crate::R<IRQ_SPEC>> for R {
-    #[inline(always)]
-    fn from(reader: crate::R<IRQ_SPEC>) -> Self {
-        R(reader)
-    }
-}
+pub type R = crate::R<IRQ_SPEC>;
 #[doc = "Register `IRQ` writer"]
-pub struct W(crate::W<IRQ_SPEC>);
-impl core::ops::Deref for W {
-    type Target = crate::W<IRQ_SPEC>;
-    #[inline(always)]
-    fn deref(&self) -> &Self::Target {
-        &self.0
-    }
-}
-impl core::ops::DerefMut for W {
-    #[inline(always)]
-    fn deref_mut(&mut self) -> &mut Self::Target {
-        &mut self.0
-    }
-}
-impl From<crate::W<IRQ_SPEC>> for W {
-    #[inline(always)]
-    fn from(writer: crate::W<IRQ_SPEC>) -> Self {
-        W(writer)
-    }
-}
+pub type W = crate::W<IRQ_SPEC>;
 #[doc = "Field `UART_1` reader - UART1 interrupt active"]
-pub type UART_1_R = crate::BitReader<bool>;
+pub type UART_1_R = crate::BitReader;
 #[doc = "Field `UART_1` writer - UART1 interrupt active"]
-pub type UART_1_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRQ_SPEC, bool, O>;
+pub type UART_1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>;
 #[doc = "Field `SPI_1` reader - SPI1 interrupt active"]
-pub type SPI_1_R = crate::BitReader<bool>;
+pub type SPI_1_R = crate::BitReader;
 #[doc = "Field `SPI_1` writer - SPI1 interrupt active"]
-pub type SPI_1_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRQ_SPEC, bool, O>;
+pub type SPI_1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>;
 #[doc = "Field `SPI_2` reader - SPI2 interrupt active"]
-pub type SPI_2_R = crate::BitReader<bool>;
+pub type SPI_2_R = crate::BitReader;
 #[doc = "Field `SPI_2` writer - SPI2 interrupt active"]
-pub type SPI_2_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRQ_SPEC, bool, O>;
+pub type SPI_2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>;
 impl R {
     #[doc = "Bit 0 - UART1 interrupt active"]
     #[inline(always)]
@@ -63,44 +31,59 @@ impl R {
         SPI_2_R::new(((self.bits >> 2) & 1) != 0)
     }
 }
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("IRQ")
+            .field("spi_2", &format_args!("{}", self.spi_2().bit()))
+            .field("spi_1", &format_args!("{}", self.spi_1().bit()))
+            .field("uart_1", &format_args!("{}", self.uart_1().bit()))
+            .finish()
+    }
+}
+impl core::fmt::Debug for crate::generic::Reg<IRQ_SPEC> {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        self.read().fmt(f)
+    }
+}
 impl W {
     #[doc = "Bit 0 - UART1 interrupt active"]
     #[inline(always)]
     #[must_use]
-    pub fn uart_1(&mut self) -> UART_1_W<0> {
+    pub fn uart_1(&mut self) -> UART_1_W<IRQ_SPEC, 0> {
         UART_1_W::new(self)
     }
     #[doc = "Bit 1 - SPI1 interrupt active"]
     #[inline(always)]
     #[must_use]
-    pub fn spi_1(&mut self) -> SPI_1_W<1> {
+    pub fn spi_1(&mut self) -> SPI_1_W<IRQ_SPEC, 1> {
         SPI_1_W::new(self)
     }
     #[doc = "Bit 2 - SPI2 interrupt active"]
     #[inline(always)]
     #[must_use]
-    pub fn spi_2(&mut self) -> SPI_2_W<2> {
+    pub fn spi_2(&mut self) -> SPI_2_W<IRQ_SPEC, 2> {
         SPI_2_W::new(self)
     }
-    #[doc = "Writes raw bits to the register."]
+    #[doc = r" Writes raw bits to the register."]
+    #[doc = r""]
+    #[doc = r" # Safety"]
+    #[doc = r""]
+    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
     #[inline(always)]
     pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
-        self.0.bits(bits);
+        self.bits = bits;
         self
     }
 }
-#[doc = "Interrupt status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [irq](index.html) module"]
+#[doc = "Interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IRQ_SPEC;
 impl crate::RegisterSpec for IRQ_SPEC {
     type Ux = u32;
 }
-#[doc = "`read()` method returns [irq::R](R) reader structure"]
-impl crate::Readable for IRQ_SPEC {
-    type Reader = R;
-}
-#[doc = "`write(|w| ..)` method takes [irq::W](W) writer structure"]
+#[doc = "`read()` method returns [`irq::R`](R) reader structure"]
+impl crate::Readable for IRQ_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`irq::W`](W) writer structure"]
 impl crate::Writable for IRQ_SPEC {
-    type Writer = W;
     const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
     const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
 }

crates/bcm2711-lpa/src/bsc0.rs

@@ -1,5 +1,6 @@
 #[doc = r"Register block"]
 #[repr(C)]
+#[derive(Debug)]
 pub struct RegisterBlock {
     #[doc = "0x00 - Control"]
     pub c: C,
@@ -18,35 +19,43 @@ pub struct RegisterBlock {
     #[doc = "0x1c - Clock stretch timeout (broken on 283x)"]
     pub clkt: CLKT,
 }
-#[doc = "C (rw) register accessor: an alias for `Reg<C_SPEC>`"]
+#[doc = "C (rw) register accessor: Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`c::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`c::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@c`]
+module"]
 pub type C = crate::Reg<c::C_SPEC>;
 #[doc = "Control"]
 pub mod c;
-#[doc = "S (rw) register accessor: an alias for `Reg<S_SPEC>`"]
+#[doc = "S (rw) register accessor: Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s`]
+module"]
 pub type S = crate::Reg<s::S_SPEC>;
 #[doc = "Status"]
 pub mod s;
-#[doc = "DLEN (rw) register accessor: an alias for `Reg<DLEN_SPEC>`"]
+#[doc = "DLEN (rw) register accessor: Data length\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dlen::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dlen::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dlen`]
+module"]
 pub type DLEN = crate::Reg<dlen::DLEN_SPEC>;
 #[doc = "Data length"]
 pub mod dlen;
-#[doc = "A (rw) register accessor: an alias for `Reg<A_SPEC>`"]
+#[doc = "A (rw) register accessor: Slave address\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`a::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`a::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@a`]
+module"]
 pub type A = crate::Reg<a::A_SPEC>;
 #[doc = "Slave address"]
 pub mod a;
-#[doc = "FIFO (rw) register accessor: an alias for `Reg<FIFO_SPEC>`"]
+#[doc = "FIFO (rw) register accessor: Data FIFO\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifo::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifo`]
+module"]
 pub type FIFO = crate::Reg<fifo::FIFO_SPEC>;
 #[doc = "Data FIFO"]
 pub mod fifo;
-#[doc = "DIV (rw) register accessor: an alias for `Reg<DIV_SPEC>`"]
+#[doc = "DIV (rw) register accessor: Clock divider\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`div::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`div::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@div`]
+module"]
 pub type DIV = crate::Reg<div::DIV_SPEC>;
 #[doc = "Clock divider"]
 pub mod div;
-#[doc = "DEL (rw) register accessor: an alias for `Reg<DEL_SPEC>`"]
+#[doc = "DEL (rw) register accessor: Data delay (Values must be under CDIV / 2)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`del::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`del::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@del`]
+module"]
 pub type DEL = crate::Reg<del::DEL_SPEC>;
 #[doc = "Data delay (Values must be under CDIV / 2)"]
 pub mod del;
-#[doc = "CLKT (rw) register accessor: an alias for `Reg<CLKT_SPEC>`"]
+#[doc = "CLKT (rw) register accessor: Clock stretch timeout (broken on 283x)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkt::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkt`]
+module"]
 pub type CLKT = crate::Reg<clkt::CLKT_SPEC>;
 #[doc = "Clock stretch timeout (broken on 283x)"]
 pub mod clkt;