SAP_1

simulation for sap 1 architecture on VHDL

First step

You put the (clk) signal in clock mode and set the (clr) signal to high to make sure the PC-program counter-clear and point to the first instruction and the SC-sequence counter-to the first step (T0) .

Second step

set the (clr) signal to low in order to make the program start.

Create Date: 20:39:28 30/05/2023

Module Name: SAP1 - Structural Project Name: SAP_1 -- Version: 1.0