My name is Zisis Katsaros and I will soon graduate with a diploma in Electrical and Computer Engineering from the Aristotle University of Thessaloniki (Greece). My interests include IC design and machine learning and through coursework and projects I have gathered fundamental experience in both fields. Currently, I am working on my thesis: prediction of Bit-Error-Rate between chiplets using a deep nural network.
Electrical and Computer Engineering under-grad at Aristotle University of Thessaloniki
- Thessaloniki, Greece
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02:07
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TinyTapeout-DMA-Controller-AUTh
TinyTapeout-DMA-Controller-AUTh PublicDMA Controller for the transfer of 8-bit words between Memory and I/O Device. Hardening through LibreLane using SKY130 PDK. Submitted to the SKY26b TinyTapeout Shuttle
Python
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Deep-Learning-Project-Winter-Sem.-2025-2026
Deep-Learning-Project-Winter-Sem.-2025-2026 PublicAristotle University of Thessaloniki, Deep-Learning Project (Winter Sem. 2025-2026): Analysis of Medical Images MedMNIST with CNN, Transfer Learning & Vision Transformers (Pytorch)
Jupyter Notebook
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deepBER
deepBER PublicMaster Thesis: Prediction of BER between Chiplets using Deep Nural Network
Python
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Opening-of-door-using-Ur10-robotic-arm
Opening-of-door-using-Ur10-robotic-arm PublicOpening of door using the Ur10 robotic arm (6 degrees of freedom).
MATLAB
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