Search results

Increase convolutional speed

Status: Open.

#34 In ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA;

· ECEVLSIWorld opened on Dec 22, 2022

The verilog project fails under higher clock frequencies (use PLL frequency multiplication 100MHz), and the FPGA output is not as expected

Status: Open.

#29 In ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA;

· MisRight opened on Apr 14, 2022

Questions about the architecture of CNN

Status: Open.

#28 In ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA;

· kangliyu1 opened on Mar 10, 2022

some questions about storage data

Status: Open.

#27 In ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA;

· kangliyu1 opened on Feb 24, 2022

Timing Simulation not working

Status: Open.

#19 In ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA;

· zee9999 opened on Nov 8, 2021

Terasic DE10-Lite

Status: Open.

#16 In ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA;

· Bahadiirr opened on Mar 25, 2021

error when run python code: r05_verilog_generator_neural_net_structure.py

Status: Open.

#13 In ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA;

· giathinhlenguyen opened on Aug 17, 2020

How to simulate the generated verilog

Status: Open.

#12 In ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA;

· ghost opened on Apr 10, 2020

modules and/or ice40 port?

Status: Open.

#10 In ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA;

· peepo opened on Jun 2, 2019

Quartus compilation failing

Status: Open.

#9 In ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA;

· JonathanKing01 opened on May 8, 2019

改变结构

Status: Open.

#8 In ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA;

· xw2333 opened on Mar 21, 2019

cam_proj.out.sdc

Status: Open.

#5 In ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA;

· hooper888 opened on Feb 19, 2019