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Merge branch 'parisc-5.9-1' of git://git.kernel.org/pub/scm/linux/ker…
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…nel/git/deller/parisc-linux

Pull parisc updates from Helge Deller:
 "The majority of the patches are reverts of previous commits regarding
  the parisc-specific low level spinlocking code and barrier handling,
  with which we tried to fix CPU stalls on our build servers. In the end
  John David Anglin found the culprit: We missed a define for
  atomic64_set_release(). This seems to have fixed our issues, so now
  it's good to remove the unnecessary code again.

  Other than that it's trivial stuff: Spelling fixes, constifications
  and such"

* 'parisc-5.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/deller/parisc-linux:
  parisc: make the log level string for register dumps const
  parisc: Do not use an ordered store in pa_tlb_lock()
  Revert "parisc: Revert "Release spinlocks using ordered store""
  Revert "parisc: Use ldcw instruction for SMP spinlock release barrier"
  Revert "parisc: Drop LDCW barrier in CAS code when running UP"
  Revert "parisc: Improve interrupt handling in arch_spin_lock_flags()"
  parisc: Replace HTTP links with HTTPS ones
  parisc: elf.h: delete a duplicated word
  parisc: Report bad pages as HardwareCorrupted
  parisc: Convert to BIT_MASK() and BIT_WORD()
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@torvalds
torvalds committed Aug 5, 2020
2 parents 4da9f33 + e2693ec commit 95ffa67
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Showing 9 changed files with 66 additions and 105 deletions.
2 changes: 1 addition & 1 deletion arch/parisc/Kconfig
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Original file line number Diff line number Diff line change
Expand Up @@ -285,7 +285,7 @@ config SMP
On a uniprocessor machine, the kernel will run faster if you say N.

See also <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO
available at <http://www.tldp.org/docs.html#howto>.
available at <https://www.tldp.org/docs.html#howto>.

If you don't know what to do here, say N.

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41 changes: 13 additions & 28 deletions arch/parisc/include/asm/bitops.h
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Original file line number Diff line number Diff line change
Expand Up @@ -12,21 +12,6 @@
#include <asm/barrier.h>
#include <linux/atomic.h>

/*
* HP-PARISC specific bit operations
* for a detailed description of the functions please refer
* to include/asm-i386/bitops.h or kerneldoc
*/

#if __BITS_PER_LONG == 64
#define SHIFT_PER_LONG 6
#else
#define SHIFT_PER_LONG 5
#endif

#define CHOP_SHIFTCOUNT(x) (((unsigned long) (x)) & (BITS_PER_LONG - 1))


/* See http://marc.theaimsgroup.com/?t=108826637900003 for discussion
* on use of volatile and __*_bit() (set/clear/change):
* *_bit() want use of volatile.
Expand All @@ -35,45 +20,45 @@

static __inline__ void set_bit(int nr, volatile unsigned long * addr)
{
unsigned long mask = 1UL << CHOP_SHIFTCOUNT(nr);
unsigned long mask = BIT_MASK(nr);
unsigned long flags;

addr += (nr >> SHIFT_PER_LONG);
addr += BIT_WORD(nr);
_atomic_spin_lock_irqsave(addr, flags);
*addr |= mask;
_atomic_spin_unlock_irqrestore(addr, flags);
}

static __inline__ void clear_bit(int nr, volatile unsigned long * addr)
{
unsigned long mask = ~(1UL << CHOP_SHIFTCOUNT(nr));
unsigned long mask = BIT_MASK(nr);
unsigned long flags;

addr += (nr >> SHIFT_PER_LONG);
addr += BIT_WORD(nr);
_atomic_spin_lock_irqsave(addr, flags);
*addr &= mask;
*addr &= ~mask;
_atomic_spin_unlock_irqrestore(addr, flags);
}

static __inline__ void change_bit(int nr, volatile unsigned long * addr)
{
unsigned long mask = 1UL << CHOP_SHIFTCOUNT(nr);
unsigned long mask = BIT_MASK(nr);
unsigned long flags;

addr += (nr >> SHIFT_PER_LONG);
addr += BIT_WORD(nr);
_atomic_spin_lock_irqsave(addr, flags);
*addr ^= mask;
_atomic_spin_unlock_irqrestore(addr, flags);
}

static __inline__ int test_and_set_bit(int nr, volatile unsigned long * addr)
{
unsigned long mask = 1UL << CHOP_SHIFTCOUNT(nr);
unsigned long mask = BIT_MASK(nr);
unsigned long old;
unsigned long flags;
int set;

addr += (nr >> SHIFT_PER_LONG);
addr += BIT_WORD(nr);
_atomic_spin_lock_irqsave(addr, flags);
old = *addr;
set = (old & mask) ? 1 : 0;
Expand All @@ -86,12 +71,12 @@ static __inline__ int test_and_set_bit(int nr, volatile unsigned long * addr)

static __inline__ int test_and_clear_bit(int nr, volatile unsigned long * addr)
{
unsigned long mask = 1UL << CHOP_SHIFTCOUNT(nr);
unsigned long mask = BIT_MASK(nr);
unsigned long old;
unsigned long flags;
int set;

addr += (nr >> SHIFT_PER_LONG);
addr += BIT_WORD(nr);
_atomic_spin_lock_irqsave(addr, flags);
old = *addr;
set = (old & mask) ? 1 : 0;
Expand All @@ -104,11 +89,11 @@ static __inline__ int test_and_clear_bit(int nr, volatile unsigned long * addr)

static __inline__ int test_and_change_bit(int nr, volatile unsigned long * addr)
{
unsigned long mask = 1UL << CHOP_SHIFTCOUNT(nr);
unsigned long mask = BIT_MASK(nr);
unsigned long oldbit;
unsigned long flags;

addr += (nr >> SHIFT_PER_LONG);
addr += BIT_WORD(nr);
_atomic_spin_lock_irqsave(addr, flags);
oldbit = *addr;
*addr = oldbit ^ mask;
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2 changes: 1 addition & 1 deletion arch/parisc/include/asm/elf.h
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Original file line number Diff line number Diff line change
Expand Up @@ -152,7 +152,7 @@
/* The following are PA function descriptors
*
* addr: the absolute address of the function
* gp: either the data pointer (r27) for non-PIC code or the
* gp: either the data pointer (r27) for non-PIC code or
* the PLT pointer (r19) for PIC code */

/* Format for the Elf32 Function descriptor */
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33 changes: 10 additions & 23 deletions arch/parisc/include/asm/spinlock.h
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Original file line number Diff line number Diff line change
Expand Up @@ -10,34 +10,25 @@
static inline int arch_spin_is_locked(arch_spinlock_t *x)
{
volatile unsigned int *a = __ldcw_align(x);
smp_mb();
return *a == 0;
}

static inline void arch_spin_lock(arch_spinlock_t *x)
{
volatile unsigned int *a;

a = __ldcw_align(x);
while (__ldcw(a) == 0)
while (*a == 0)
cpu_relax();
}
#define arch_spin_lock(lock) arch_spin_lock_flags(lock, 0)

static inline void arch_spin_lock_flags(arch_spinlock_t *x,
unsigned long flags)
{
volatile unsigned int *a;
unsigned long flags_dis;

a = __ldcw_align(x);
while (__ldcw(a) == 0) {
local_save_flags(flags_dis);
local_irq_restore(flags);
while (__ldcw(a) == 0)
while (*a == 0)
cpu_relax();
local_irq_restore(flags_dis);
}
if (flags & PSW_SM_I) {
local_irq_enable();
cpu_relax();
local_irq_disable();
} else
cpu_relax();
}
#define arch_spin_lock_flags arch_spin_lock_flags

Expand All @@ -46,12 +37,8 @@ static inline void arch_spin_unlock(arch_spinlock_t *x)
volatile unsigned int *a;

a = __ldcw_align(x);
#ifdef CONFIG_SMP
(void) __ldcw(a);
#else
mb();
#endif
*a = 1;
/* Release with ordered store. */
__asm__ __volatile__("stw,ma %0,0(%1)" : : "r"(1), "r"(a) : "memory");
}

static inline int arch_spin_trylock(arch_spinlock_t *x)
Expand Down
48 changes: 25 additions & 23 deletions arch/parisc/kernel/entry.S
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Original file line number Diff line number Diff line change
Expand Up @@ -454,7 +454,6 @@
nop
LDREG 0(\ptp),\pte
bb,<,n \pte,_PAGE_PRESENT_BIT,3f
LDCW 0(\tmp),\tmp1
b \fault
stw \spc,0(\tmp)
99: ALTERNATIVE(98b, 99b, ALT_COND_NO_SMP, INSN_NOP)
Expand All @@ -464,23 +463,26 @@
3:
.endm

/* Release pa_tlb_lock lock without reloading lock address. */
.macro tlb_unlock0 spc,tmp,tmp1
/* Release pa_tlb_lock lock without reloading lock address.
Note that the values in the register spc are limited to
NR_SPACE_IDS (262144). Thus, the stw instruction always
stores a nonzero value even when register spc is 64 bits.
We use an ordered store to ensure all prior accesses are
performed prior to releasing the lock. */
.macro tlb_unlock0 spc,tmp
#ifdef CONFIG_SMP
98: or,COND(=) %r0,\spc,%r0
LDCW 0(\tmp),\tmp1
or,COND(=) %r0,\spc,%r0
stw \spc,0(\tmp)
stw,ma \spc,0(\tmp)
99: ALTERNATIVE(98b, 99b, ALT_COND_NO_SMP, INSN_NOP)
#endif
.endm

/* Release pa_tlb_lock lock. */
.macro tlb_unlock1 spc,tmp,tmp1
.macro tlb_unlock1 spc,tmp
#ifdef CONFIG_SMP
98: load_pa_tlb_lock \tmp
99: ALTERNATIVE(98b, 99b, ALT_COND_NO_SMP, INSN_NOP)
tlb_unlock0 \spc,\tmp,\tmp1
tlb_unlock0 \spc,\tmp
#endif
.endm

Expand Down Expand Up @@ -1163,7 +1165,7 @@ dtlb_miss_20w:

idtlbt pte,prot

tlb_unlock1 spc,t0,t1
tlb_unlock1 spc,t0
rfir
nop

Expand All @@ -1189,7 +1191,7 @@ nadtlb_miss_20w:

idtlbt pte,prot

tlb_unlock1 spc,t0,t1
tlb_unlock1 spc,t0
rfir
nop

Expand Down Expand Up @@ -1223,7 +1225,7 @@ dtlb_miss_11:

mtsp t1, %sr1 /* Restore sr1 */

tlb_unlock1 spc,t0,t1
tlb_unlock1 spc,t0
rfir
nop

Expand Down Expand Up @@ -1256,7 +1258,7 @@ nadtlb_miss_11:

mtsp t1, %sr1 /* Restore sr1 */

tlb_unlock1 spc,t0,t1
tlb_unlock1 spc,t0
rfir
nop

Expand Down Expand Up @@ -1285,7 +1287,7 @@ dtlb_miss_20:

idtlbt pte,prot

tlb_unlock1 spc,t0,t1
tlb_unlock1 spc,t0
rfir
nop

Expand Down Expand Up @@ -1313,7 +1315,7 @@ nadtlb_miss_20:

idtlbt pte,prot

tlb_unlock1 spc,t0,t1
tlb_unlock1 spc,t0
rfir
nop

Expand Down Expand Up @@ -1420,7 +1422,7 @@ itlb_miss_20w:

iitlbt pte,prot

tlb_unlock1 spc,t0,t1
tlb_unlock1 spc,t0
rfir
nop

Expand All @@ -1444,7 +1446,7 @@ naitlb_miss_20w:

iitlbt pte,prot

tlb_unlock1 spc,t0,t1
tlb_unlock1 spc,t0
rfir
nop

Expand Down Expand Up @@ -1478,7 +1480,7 @@ itlb_miss_11:

mtsp t1, %sr1 /* Restore sr1 */

tlb_unlock1 spc,t0,t1
tlb_unlock1 spc,t0
rfir
nop

Expand All @@ -1502,7 +1504,7 @@ naitlb_miss_11:

mtsp t1, %sr1 /* Restore sr1 */

tlb_unlock1 spc,t0,t1
tlb_unlock1 spc,t0
rfir
nop

Expand Down Expand Up @@ -1532,7 +1534,7 @@ itlb_miss_20:

iitlbt pte,prot

tlb_unlock1 spc,t0,t1
tlb_unlock1 spc,t0
rfir
nop

Expand All @@ -1552,7 +1554,7 @@ naitlb_miss_20:

iitlbt pte,prot

tlb_unlock1 spc,t0,t1
tlb_unlock1 spc,t0
rfir
nop

Expand Down Expand Up @@ -1582,7 +1584,7 @@ dbit_trap_20w:

idtlbt pte,prot

tlb_unlock0 spc,t0,t1
tlb_unlock0 spc,t0
rfir
nop
#else
Expand All @@ -1608,7 +1610,7 @@ dbit_trap_11:

mtsp t1, %sr1 /* Restore sr1 */

tlb_unlock0 spc,t0,t1
tlb_unlock0 spc,t0
rfir
nop

Expand All @@ -1628,7 +1630,7 @@ dbit_trap_20:

idtlbt pte,prot

tlb_unlock0 spc,t0,t1
tlb_unlock0 spc,t0
rfir
nop
#endif
Expand Down
3 changes: 3 additions & 0 deletions arch/parisc/kernel/pdt.c
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Original file line number Diff line number Diff line change
Expand Up @@ -18,6 +18,8 @@
#include <linux/kthread.h>
#include <linux/initrd.h>
#include <linux/pgtable.h>
#include <linux/swap.h>
#include <linux/swapops.h>

#include <asm/pdc.h>
#include <asm/pdcpat.h>
Expand Down Expand Up @@ -230,6 +232,7 @@ void __init pdc_pdt_init(void)

/* mark memory page bad */
memblock_reserve(pdt_entry[i] & PAGE_MASK, PAGE_SIZE);
num_poisoned_pages_inc();
}
}

Expand Down
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