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add e907 spi adc twi driver
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@YuzukiTsuru
YuzukiTsuru committed Jul 24, 2023
1 parent aef1aa9 commit 7a0166c
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Showing 46 changed files with 6,650 additions and 910 deletions.
1 change: 0 additions & 1 deletion Software/BSP/e907_rtos/rtos-hal/hal/include
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This file was deleted.

4 changes: 3 additions & 1 deletion Software/BSP/e907_rtos/rtos-hal/hal/source/Makefile
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@@ -1,9 +1,11 @@
obj-$(CONFIG_DRIVERS_CCMU) += ccmu/
obj-$(CONFIG_DRIVERS_UART) += uart/
obj-$(CONFIG_DRIVERS_RTC) += rtc/
obj-$(CONFIG_DRIVERS_SPI) += spi/
obj-$(CONFIG_DRIVERS_GPIO) += gpio/
obj-$(CONFIG_DRIVERS_DMA) += dma/
obj-$(CONFIG_DRIVERS_TWI) += twi/
obj-$(CONFIG_DRIVERS_PWM) += pwm/
obj-$(CONFIG_DRIVERS_GPADC) += gpadc/
obj-$(CONFIG_DRIVERS_MSGBOX) += msgbox/
obj-y += common/
obj-y += common/
1 change: 1 addition & 0 deletions Software/BSP/e907_rtos/rtos-hal/hal/source/ccmu/common_ccmu.h
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Expand Up @@ -81,6 +81,7 @@ typedef enum
#if defined(CONFIG_DRIVERS_SUNXI_CLK)

#define HAL_SUNXI_CCU (0)
#define HAL_SUNXI_FIXED_CCU (1)

#include "sunxi/clk.h"
typedef hal_clk_id_t hal_clk_t;
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9 changes: 6 additions & 3 deletions Software/BSP/e907_rtos/rtos-hal/hal/source/ccmu/sunxi/clk.c
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Expand Up @@ -523,10 +523,11 @@ hal_clk_status_t sunxi_clk_get_rate(hal_clk_id_t clk, u32 *rate)

hal_clk_status_t sunxi_clk_set_rate(hal_clk_id_t clk, u32 rate)
{
u32 i, parent_rate;
u32 i;
clk_core_pt pclk = NULL;
clk_periph_pt periph_clk = NULL;
clk_factor_pt factor_clk = NULL;
clk_core_pt parent_clk_core = NULL;
hal_clk_status_t ret = HAL_CLK_STATUS_ERROR_CLK_NOT_FOUND;

CCMU_TRACE();
Expand All @@ -550,8 +551,10 @@ hal_clk_status_t sunxi_clk_set_rate(hal_clk_id_t clk, u32 rate)
{
return HAL_CLK_STATUS_OK;
}
parent_rate = periph_clk->clk_core.parent_rate;
ret = sunxi_clk_periph_set_rate(periph_clk, rate);
parent_clk_core = clk_get_core(periph_clk->clk_core.current_parent);
periph_clk->clk_core.parent_rate = parent_clk_core->clk_rate;

ret = sunxi_clk_periph_set_rate(periph_clk, rate);
if (ret == HAL_CLK_STATUS_OK)
{
periph_clk->clk_core.clk_rate = rate;
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6 changes: 6 additions & 0 deletions Software/BSP/e907_rtos/rtos-hal/hal/source/ccmu/sunxi/platform_clk.h
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Expand Up @@ -70,6 +70,11 @@ enum
HAL_CLK_PLL_AUDIOX2,
HAL_CLK_PLL_AUDIOX4,
HAL_CLK_PLL_DDRDIV4,
HAL_HOSC_DIV32,
HAL_HOSC_DIV16,
HAL_HOSC_DIV8,
HAL_HOSC_DIV4,
HAL_HOSC_DIV2,
HAL_CLK_PLL_NPUX2,
HAL_CLK_PLL_NPU,
HAL_CLK_HOSCD2,
Expand Down Expand Up @@ -359,6 +364,7 @@ enum
HAL_CLK_PLL_CVE,
HAL_CLK_PLL_ISE,
HAL_CLK_PLL_CSI,
HAL_CLK_PLL_CSIX4,

/*
PERIPH MODULE CLOCK 1024~2047
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16 changes: 12 additions & 4 deletions Software/BSP/e907_rtos/rtos-hal/hal/source/ccmu/sunxi/sun8iw21p1/clk_sun8iw21.c
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Expand Up @@ -547,6 +547,7 @@ PLLVIDEO0(98, 1, 1188000000U),
/* PLL_CSI(n, d1, freq) F_N8X8_D1V1X1 */
struct sunxi_clk_factor_freq factor_pllcsix4_tbl[] = {
PLLCSI(98, 1, 1188000000U),
PLLCSI(98, 0, 2376000000U),
};

/* PLLAUDIO(n, p, d1, d2, freq) F_N8X8_P16X6_D1V1X1_D2V0X1 */
Expand Down Expand Up @@ -591,11 +592,17 @@ SUNXI_CLK_FIXED_FACTOR(pll_npu, HAL_CLK_PLL_NPU, HAL_CLK_PLL_NPUX4, HAL_CLK_FACT
SUNXI_CLK_FIXED_FACTOR(hoscd2, HAL_CLK_HOSCD2, HAL_CLK_SRC_HOSC, HAL_CLK_FACTOR, 1, 2);
SUNXI_CLK_FIXED_FACTOR(osc48md4, HAL_CLK_OSC48MD4, HAL_CLK_SRC_OSC48M, HAL_CLK_FACTOR, 1, 4);
SUNXI_CLK_FIXED_FACTOR(sdramd4, HAL_CLK_SDRAMD4, HAL_CLK_PERIPH_SDRAM, HAL_CLK_FACTOR, 1, 4);
SUNXI_CLK_FIXED_FACTOR(hosc_div32, HAL_HOSC_DIV32, HAL_CLK_SRC_HOSC, HAL_CLK_FACTOR, 1, 32);
SUNXI_CLK_FIXED_FACTOR(hosc_div16, HAL_HOSC_DIV16, HAL_CLK_SRC_HOSC, HAL_CLK_FACTOR, 1, 16);
SUNXI_CLK_FIXED_FACTOR(hosc_div8, HAL_HOSC_DIV8, HAL_CLK_SRC_HOSC, HAL_CLK_FACTOR, 1, 8);
SUNXI_CLK_FIXED_FACTOR(hosc_div4, HAL_HOSC_DIV4, HAL_CLK_SRC_HOSC, HAL_CLK_FACTOR, 1, 4);
SUNXI_CLK_FIXED_FACTOR(hosc_div2, HAL_HOSC_DIV2, HAL_CLK_SRC_HOSC, HAL_CLK_FACTOR, 1, 2);


/* name, ns nw ks kw ms mw ps pw d1s d1w d2s d2w {frac out mode} en-s sdmss sdmsw sdmpat sdmval mux_in-s out_en-s*/
SUNXI_CLK_FACTORS_CONFIG(pll_cpu, 8, 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 31, 0, 0, 0, 0, 23, 27);
SUNXI_CLK_FACTORS_CONFIG(pll_ddr0, 8, 8, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 31, 24, 1, CLK_PLL_DDRPAT, 0xd1303333, 23, 27);
SUNXI_CLK_FACTORS_CONFIG(pll_periph0x2, 8, 8, 0, 0, 1, 1, 0, 0, 16, 3, 0, 0, 0, 0, 0, 31, 24, 1, CLK_PLL_PERI0PAT0, 0xd1303333, 23, 27);
SUNXI_CLK_FACTORS_CONFIG(pll_periph0x2, 8, 8, 0, 0, 1, 1, 0, 0, 16, 3, 0, 0, 0, 0, 0, 31, 24, 0, CLK_PLL_PERI0PAT0, 0xd1303333, 23, 27);
SUNXI_CLK_FACTORS_CONFIG(pll_periph0800m, 8, 8, 0, 0, 1, 1, 0, 0, 20, 3, 0, 0, 0, 0, 0, 31, 24, 1, CLK_PLL_PERI0PAT0, 0xd1303333, 23, 27);
SUNXI_CLK_FACTORS_CONFIG(pll_periph0480m, 8, 8, 0, 0, 1, 1, 0, 0, 2, 3, 0, 0, 0, 0, 0, 31, 24, 1, CLK_PLL_PERI0PAT0, 0xd1303333, 23, 27);
SUNXI_CLK_FACTORS_CONFIG(pll_video0x4, 8, 8, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 31, 24, 1, CLK_PLL_VIDEO0PAT0, 0xd1303333, 23, 27);
Expand Down Expand Up @@ -662,6 +669,7 @@ hal_clk_id_t fanout12m_parents[] = {HAL_CLK_HOSCD2};
hal_clk_id_t fanout24m_parents[] = {HAL_CLK_SRC_HOSC};
hal_clk_id_t fanout27m_parents[] = {HAL_CLK_PLL_AUDIO, HAL_CLK_PLL_CSI, HAL_CLK_PLL_PERI0300M};
hal_clk_id_t fanout_pclk_parents[] = {HAL_CLK_BUS_APB0};
hal_clk_id_t gpadc_parents[] = {HAL_HOSC_DIV32, HAL_HOSC_DIV16, HAL_HOSC_DIV8, HAL_HOSC_DIV4, HAL_HOSC_DIV2, HAL_CLK_SRC_HOSC};
hal_clk_id_t fanout012_parents[] = {HAL_CLK_SRC_LOSC_OUT, HAL_CLK_PERIPH_FANOUT_12M, HAL_CLK_PERIPH_FANOUT_16M, HAL_CLK_PERIPH_FANOUT_24M, HAL_CLK_PERIPH_FANOUT_25M, HAL_CLK_PERIPH_FANOUT_27M, HAL_CLK_PERIPH_FANOUT_PCLK};

hal_clk_id_t ahbmod_parents[] = {HAL_CLK_BUS_AHB};
Expand Down Expand Up @@ -726,7 +734,7 @@ SUNXI_CLK_PERIPH_CONFIG(spi3, CLK_SPI3_CFG, 24, 3,
SUNXI_CLK_PERIPH_CONFIG(spif, CLK_SPIF_CFG, 24, 3, CLK_SPIF_CFG, 0, 4, 8, 2, 0, CLK_SPI3_CFG, CLK_SPI_GATE, CLK_SPI_GATE, 0, 31, 20, 4, 0, NULL, 0);
SUNXI_CLK_PERIPH_CONFIG(gmac_25m, 0, 0, 0, 0, 0, 0, 0, 0, 0, CLK_GMAC25M_CFG, 0, CLK_GMAC25M_CFG, 0, 31, 0, 30, 0, NULL, 0);
SUNXI_CLK_PERIPH_CONFIG(gmac, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, CLK_GMAC_GATE, CLK_GMAC_GATE, 0, 0, 16, 0, 0, NULL, 0);
SUNXI_CLK_PERIPH_CONFIG(gpadc, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, CLK_GPADC_GATE, CLK_GPADC_GATE, 0, 0, 16, 0, 0, NULL, 0);
SUNXI_CLK_PERIPH_CONFIG(gpadc, CLK_GPADC_SEL, 22, 3, 0, 0, 0, 0, 0, 0, 0, CLK_GPADC_GATE, CLK_GPADC_GATE, 0, 0, 16, 0, 0, NULL, 0);
SUNXI_CLK_PERIPH_CONFIG(ths, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, CLK_THS_GATE, CLK_THS_GATE, 0, 0, 16, 0, 0, NULL, 0);
SUNXI_CLK_PERIPH_CONFIG(pll_audiox4, 0, 0, 0, CLK_PLL_PRE_CFG, 5, 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, NULL, 0);
SUNXI_CLK_PERIPH_CONFIG(pll_audio, 0, 0, 0, CLK_PLL_PRE_CFG, 0, 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, NULL, 0);
Expand Down Expand Up @@ -809,7 +817,7 @@ SUNXI_CLK_PERIPH(spi3, HAL_CLK_PERIPH_SPI3, spi_parents);
SUNXI_CLK_PERIPH(spif, HAL_CLK_PERIPH_SPIF, spi_parents);
SUNXI_CLK_PERIPH(gmac_25m, HAL_CLK_PERIPH_GMAC_25M, gmac_25m_parents);
SUNXI_CLK_PERIPH(gmac, HAL_CLK_PERIPH_GMAC, ahbmod_parents);
SUNXI_CLK_PERIPH(gpadc, HAL_CLK_PERIPH_GPADC, apb0mod_parents);
SUNXI_CLK_PERIPH(gpadc, HAL_CLK_PERIPH_GPADC, gpadc_parents);
SUNXI_CLK_PERIPH(ths, HAL_CLK_PERIPH_THS, apb0mod_parents);
/*
* Strictly speaking, the pll_audiox4 and pll_audio are not pll clocks, although they are called pll
Expand Down Expand Up @@ -1149,7 +1157,7 @@ static int calc_rate_pll_csix4(u32 parent_rate,
{
u64 tmp_rate = (parent_rate ? parent_rate : 24000000);
tmp_rate = tmp_rate * (factor->factorn + 1);
do_div(tmp_rate, 4 * (factor->factord1 + 1));
do_div(tmp_rate, (factor->factord1 + 1));
return (u32)tmp_rate;
}

Expand Down
3 changes: 2 additions & 1 deletion Software/BSP/e907_rtos/rtos-hal/hal/source/ccmu/sunxi/sun8iw21p1/clk_sun8iw21.h
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Expand Up @@ -46,7 +46,7 @@
#define SUNXI_CLK_FACTOR_PERIPH0800M_MAX_FREQ (1200000000U)
#define SUNXI_CLK_FACTOR_PERIPH0480M_MAX_FREQ (1200000000U)
#define SUNXI_CLK_FACTOR_VIDEO0X4_MAX_FREQ (1188000000U)
#define SUNXI_CLK_FACTOR_CSIX4_MAX_FREQ (1188000000U)
#define SUNXI_CLK_FACTOR_CSIX4_MAX_FREQ (2376000000U)
#define SUNXI_CLK_FACTOR_AUDIO_MAX_FREQ (288000000U)
#define SUNXI_CLK_FACTOR_NPUX4_MAX_FREQ (1188000000U)

Expand Down Expand Up @@ -162,6 +162,7 @@
#define CLK_E907_CFG (volatile uint32_t *)(CCU_REG_BASE + 0x0D00)
#define CLK_RISCV_GATE (volatile uint32_t *)(CCU_REG_BASE + 0x0D0C)
#define CLK_PLL_PRE_CFG (volatile uint32_t *)(CCU_REG_BASE + 0x0E00)
#define CLK_GPADC_SEL (volatile uint32_t *)(CCU_REG_BASE + 0x0F04)
#define CLK_FANOUT_GATE (volatile uint32_t *)(CCU_REG_BASE + 0x0F30)
#define CLK_FANOUT27M_CFG (volatile uint32_t *)(CCU_REG_BASE + 0x0F34)
#define CLK_FANOUTPCLK_CFG (volatile uint32_t *)(CCU_REG_BASE + 0x0F38)
Expand Down
12 changes: 12 additions & 0 deletions Software/BSP/e907_rtos/rtos-hal/hal/source/gpadc/Kconfig
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@@ -0,0 +1,12 @@
menu "GPADC Devices"

config DRIVERS_GPADC
bool "enable gpadc driver"
default y

config HAL_TEST_GPADC
bool "enable gpadc hal APIs test command"
depends on DRIVERS_GPADC
default n

endmenu
1 change: 1 addition & 0 deletions Software/BSP/e907_rtos/rtos-hal/hal/source/gpadc/Makefile
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@@ -0,0 +1 @@
obj-y += hal_gpadc.o
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