[board] refactor directory, add init-dram case on 100ask-d1-h

Minor fixes to xtask module.

Signed-off-by: DongQing <placebo27@hust.edu.cn>

board/100ask-d1-h-rs/Cargo.toml

@@ -16,7 +16,12 @@ allwinner-rt = { git = "https://github.com/rustsbi/allwinner-hal" }
 embedded-hal = "1.0.0"
 embedded-io = "0.6.1"
 
-[[bin]]
-name = "syterkit-100ask-d1-h"
+[lib]
+name = "syterkit_100ask_d1_h"
 test = false
 bench = false
+
+[features]
+default = ["nezha"]
+nezha = []
+lichee = []

board/100ask-d1-h-rs/build.rs

@@ -1,3 +1,3 @@
 fn main() {
     println!("cargo:rustc-link-arg=-Tallwinner-rt.ld");
-}
+}

board/100ask-d1-h-rs/src/bin/init-dram.rs

@@ -0,0 +1,18 @@
+#![no_std]
+#![no_main]
+use allwinner_hal::uart::{Config, Serial};
+use allwinner_rt::{entry, Clocks, Peripherals};
+use embedded_io::Write;
+use panic_halt as _;
+use syterkit_100ask_d1_h::mctl;
+
+#[entry]
+fn main(p: Peripherals, c: Clocks) {
+    let tx = p.gpio.pb8.into_function::<6>();
+    let rx = p.gpio.pb9.into_function::<6>();
+    let mut serial = Serial::new(p.uart0, (tx, rx), Config::default(), &c, &p.ccu);
+
+    writeln!(serial, "DDR init").unwrap();
+    let ram_size = mctl::init();
+    writeln!(serial, "{}M 🐏", ram_size).unwrap();
+}

board/100ask-d1-h-rs/src/lib.rs

@@ -0,0 +1,3 @@
+#![no_std]
+
+pub mod mctl;