Don't sort anything ever

[widlarizer]

This PR adds one small commit on top of #5315. That commit removes design->sort(); from all passes that unconditionally run it. I believe Yosys is deterministic with reproducible results with or without those. If abc isn't, then that's a more impactful problem than can be saved by sorting at any point in the flow.

The only test that ultimately has to be fixed with this change is tests/arch/xilinx/dsp_cascade.ys where the reordering of the design changes the count of some FDRE primitives received by synthesis. This change also greatly increases the runtime of equiv_opt in that one test despite the size of the SAT problem being exactly the same. Reduced reproducer for this slowdown:

design -reset
read_verilog <<EOT
module cascade(input clk, input [4:0] a, input [4:0] b, output reg [9:0] o);
reg [4:0] ar1, ar2, ar3, br1, br2, br3;
reg [9:0] m, n;
always @(posedge clk) begin
ar1 <= a;
ar2 <= ar1;
ar3 <= ar2;
br1 <= b;
br2 <= br1;
br3 <= br2;
m <= ar1 * br1;
n <= ar2 * br2 + m;
o <= ar3 * br3 + n;
end
endmodule
EOT
proc
design -save read

equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad

This speeds up running synth on jpeg by 5%, tested with 3 different values for --hash-idx. It also likely makes --hash-idx a more powerful hyper-optimization input.