QuickLogic DSPv2 support #4932
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QuickLogic DSPv2 support #4932
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…n model unchanged
Add support for cell type dispatching of the new DSP block; adjust the definition of MULT and MULTACC variants to support those instances starting a cascading chain.
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What are the reasons/motivation for this change?
Add support for v2 DSP block per a simulation model provided by QuickLogic. Support mapping basic multiplication operation, multiply-accumulate pattern, input and output register packing, sum-of-products cascading.
Explain how this is achieved.
Build a flow analogous to v1 DSP support, borrow pattern matcher bits from Xilinx flow.
If applicable, please suggest to reviewers how they can test the change.
Tests attached
Before we merge: