read_liberty: Optionally import unit delay arcs

[povik]

What are the reasons/motivation for this change?

Avoiding timing path segmentation on explicitly instantiated or pre-mapped standard cells. When the SC mapper is configured for the unit delay model, with this new option we can supply complementary arcs for those cells which are viewed as boxes

Explain how this is achieved.

Under each cell and pin, we look at timing() sections with timing_type set to combinational, and for each arc found, we emit a $specify2 cell with fixed delay of 1000 which matches the unit delay inside ABC.

[povik]

This is an almost empty test since we don't have any .lib files checked in with populated timing sections. We can find a new one provided the licensing is ok