read_liberty: Optionally import unit delay arcs #4605
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povik
commented
Sep 18, 2024
| @@ -0,0 +1,3 @@ | |||
| # Nothing gets imported: the file lacks timing data | |||
| read_liberty -wb -unit_delay normal.lib | |||
| select -assert-none =*/t:$specify* | |||
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This is an almost empty test since we don't have any .lib files checked in with populated timing sections. We can find a new one provided the licensing is ok
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What are the reasons/motivation for this change?
Avoiding timing path segmentation on explicitly instantiated or pre-mapped standard cells. When the SC mapper is configured for the unit delay model, with this new option we can supply complementary arcs for those cells which are viewed as boxes
Explain how this is achieved.
Under each cell and pin, we look at
timing()sections withtiming_typeset tocombinational, and for each arc found, we emit a$specify2cell with fixed delay of 1000 which matches the unit delay inside ABC.