Add several new formatting features used by Amaranth to translate Python format strings #4301
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@mmicko I need to have these in the next Yosys release to meet the current Amaranth release schedule. The PR should be done by the 1st or very shortly after. |
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This looks like it overlaps or supersedes #4192. |
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@povik I think there's actually no overlap? Note |
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Right you are |
Before this commit, the `STRING` variant inserted a literal string; the `CHARACTER` variant inserted a string. This commit renames them to `LITERAL` and `STRING` respectively.
This is necessary for translating Python format strings in Amaranth.
The first two were already supported with the `plus` boolean flag. The third one is a new specifier, which is allocated the ` ` character. In addition, `MINUS` is now allocated the `-` character, but old format where there is no `+`, `-`, or `-` in the respective position is also accepted for compatibility.
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Before this commit, the existing alignments were `LEFT` and `RIGHT`, which added the `padding` character to the right and left just before finishing formatting. However, if `padding == '0'` and the alignment is to the right, then the padding character (digit zero) was added after the sign, if one is present. After this commit, the special case for `padding == '0'` is removed, and the new justification `NUMERIC` adds the padding character like the justification `RIGHT`, except after the sign, if one is present. (Space, for the `SPACE_MINUS` sign mode, counts as the sign.)
This format type is used to print an Unicode character (code point) as its UTF-8 serialization. To this end, two UTF-8 decoders (one for fmt, one for cxxrtl) are added for rendering. When converted to a Verilog format specifier, `UNICHAR` degrades to `%c` with the low 7 bits of the code point, which has equivalent behavior for inputs not exceeding ASCII. (SystemVerilog leaves source and display encodings completely undefined.)
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The option is serialized to RTLIL as `#` (to match Python's and Rust's option with the same symbol), and sets the `show_base` flag. Because the flag is called `show_base` and not e.g. `alternate_format` (which is what Python and Rust call it), in addition to the prefixes `0x`, `0X`, `0o`, `0b`, the RTLIL option also prints the `0d` prefix.
The option is serialized to RTLIL as `_` (to match Python's option with the same symbol), and sets the `group` flag. This flag inserts an `_` symbol between each group of 3 digits (for decimal) or four digits (for binary, hex, and octal).
Also fix interaction of `NUMERIC` justification with `show_base`.
When converted to Verilog, padding characters are replaced with one of these two. Otherwise padding is performed with exactly that character.
Before this commit, the combination of `_` and `0` format characters
would produce a result like `000000001010_1010`.
After this commit, it would be `0000_0000_1010_1010`.
This has a slight quirk where a format like `{:020_b}` results in
the output `0_0000_0000_1010_1010`, which is one character longer than
requested. Python has the same behavior, and it's not clear what would
be strictly speaking correct, so Python behavior is implemented.
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This is a work-in-progress PR at the moment.
Hformat type (uppercase hex digits)cformat type (Unicode code point emitted as UTF-8)=justification (align right, but after the padding)-or-or+)_option (insert an underscore between each 3 decimal, 4 binary/octal/hex digits)#option (insert0x/0o/0bafter sign and before padding)0padding and_