Zero-width source attribute with synth -noabc

[widlarizer]

Version

0.45 or main

On which OS did this happen?

Linux

Reproduction Steps

module alu(
	input clk,
	input A,
	input [1:0] operation,
	output reg [7:0] result
);
	always @(posedge clk)
	begin
		case (operation)
			1 :
				result = { A, 1'b0};
			2 :
				result = { A, 1'b0};
		endcase
	end
endmodule

read_verilog tests/sat/alu.v; synth -noabc; dump

Expected Behavior

src attribute values make sense

Actual Behavior

There is a zero-width 0'x src attribute: attribute \src 0'x

[widlarizer]

This is due to lines like gate->attributes[ID::src] = cell->attributes[ID::src]; in simplemap adding default constructed Consts when mapping cells that had no src attribute