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Description
Version
main
On which OS did this happen?
Linux
Reproduction Steps
Liberty file format allows the specification of the value internal variables attain when a DFFSR is being both set and reset with variables clear_preset_var1
and clear_preset_var2
. Yosys internal cells canonically prioritize reset over set in all DFFSR and dfflibmap
ignores the relevant liberty variables clear_preset_var1
and clear_preset_var2
.
Some examples of the interpretation of these cells:
- async2sync - reset has priority
- verilog, proc_dff - no assumption about s&r behavior
- dfflibmap - assumes s&r behavior is free to be replaced with any other (disrespects
clear_preset_var*
) - read_liberty - incorrectly always presents liberty dffsr as "reset has priority" (disrespects
clear_preset_var*
) - filterlib -verilogsim - correctly models liberty cell behavior (respects
clear_preset_var*
)
Expected Behavior
Either:
- documentation declares dffsr cells to have an undefined output and state when
set&reset
- or dfflibmap gets way more complex and worse at mapping because it only picks cells with matching
set&reset
behavior - or we add more internal flop cell types or parameters to be able to specify this behavior
Actual Behavior
Some passes secretly assume a different definition of $dffsr
and related cells than is documented