Fuzzed missing SLICE connection timings

YosysHQ · Sep 22, 2023 · fde6e70 · fde6e70
1 parent 9d8d68b
commit fde6e70
Show file tree

Hide file tree

Showing 4 changed files with 19 additions and 3 deletions.
diff --git a/timing/fuzzers/MachXO2/010-basic-cells/fuzzer.py b/timing/fuzzers/MachXO2/010-basic-cells/fuzzer.py
@@ -9,7 +9,7 @@ def rewrite_celltype_XO2(name, type):
     return type.split('/')[-1].split("_")[0]
 
 def main():
-    cell_fuzzers.build_and_add(["../../../resource/picorv32_large.v", "../../../resource/picorv32_large_blockram.v", "../../../resource/distributed_ram.v", "../../../resource/altair.v", "../../../resource/jt49.v", "../../../resource/jt5205.v", "../../../resource/jt7759.v"], density="7000", family="MachXO2", inc_cell=include_cell_XO2, rw_cell_func=rewrite_celltype_XO2)
+    cell_fuzzers.build_and_add(["../../../resource/picorv32_large.v", "../../../resource/picorv32_large_blockram.v", "../../../resource/distributed_ram.v", "../../../resource/altair.v", "../../../resource/jt49.v", "../../../resource/jt5205.v", "../../../resource/jt7759.v", "../../../resource/math.v"], density="7000", family="MachXO2", inc_cell=include_cell_XO2, rw_cell_func=rewrite_celltype_XO2)
 
 
 if __name__ == "__main__":

diff --git a/timing/fuzzers/MachXO3/010-basic-cells/fuzzer.py b/timing/fuzzers/MachXO3/010-basic-cells/fuzzer.py
@@ -9,7 +9,7 @@ def rewrite_celltype_XO3(name, type):
     return type.split('/')[-1].split("_")[0]
 
 def main():
-    cell_fuzzers.build_and_add(["../../../resource/picorv32_large.v", "../../../resource/picorv32_large_blockram.v", "../../../resource/distributed_ram.v", "../../../resource/altair.v", "../../../resource/jt49.v", "../../../resource/jt5205.v", "../../../resource/jt7759.v"], density="6900", family="MachXO3", inc_cell=include_cell_XO3, rw_cell_func=rewrite_celltype_XO3)
+    cell_fuzzers.build_and_add(["../../../resource/picorv32_large.v", "../../../resource/picorv32_large_blockram.v", "../../../resource/distributed_ram.v", "../../../resource/altair.v", "../../../resource/jt49.v", "../../../resource/jt5205.v", "../../../resource/jt7759.v", "../../../resource/math.v"], density="6900", family="MachXO3", inc_cell=include_cell_XO3, rw_cell_func=rewrite_celltype_XO3)
 
 
 if __name__ == "__main__":

diff --git a/timing/fuzzers/MachXO3D/010-basic-cells/fuzzer.py b/timing/fuzzers/MachXO3D/010-basic-cells/fuzzer.py
@@ -9,7 +9,7 @@ def rewrite_celltype_XO3D(name, type):
     return type.split('/')[-1].split("_")[0]
 
 def main():
-    cell_fuzzers.build_and_add(["../../../resource/picorv32_large.v", "../../../resource/picorv32_large_blockram.v", "../../../resource/distributed_ram.v", "../../../resource/altair.v", "../../../resource/jt49.v", "../../../resource/jt5205.v", "../../../resource/jt7759.v"], density="9400", family="MachXO3D", inc_cell=include_cell_XO3D, rw_cell_func=rewrite_celltype_XO3D)
+    cell_fuzzers.build_and_add(["../../../resource/picorv32_large.v", "../../../resource/picorv32_large_blockram.v", "../../../resource/distributed_ram.v", "../../../resource/altair.v", "../../../resource/jt49.v", "../../../resource/jt5205.v", "../../../resource/jt7759.v", "../../../resource/math.v"], density="9400", family="MachXO3D", inc_cell=include_cell_XO3D, rw_cell_func=rewrite_celltype_XO3D)
 
 
 if __name__ == "__main__":

diff --git a/timing/resource/math.v b/timing/resource/math.v
@@ -0,0 +1,16 @@
+module top (
+	input clk,
+	input [31:0] a,
+	input [31:0] b,
+    input [7:0] c,
+
+	output reg [63:0] d
+);
+
+    reg [63:0] tmp;
+	always @(posedge clk) begin
+        tmp <= tmp + 123323;
+		d <= (a + b) * c + tmp;
+	end
+
+endmodule