Basic timing fuzzers for XO2 and XO3D

timing/fuzzers/MachXO2/010-basic-cells/fuzzer.py

@@ -0,0 +1,16 @@
+import cell_fuzzers
+
+def include_cell_XO2(name, type):
+    type = type.split('/')[-1].split("_")[0]
+    return type.isupper() and "_" not in type
+
+
+def rewrite_celltype_XO2(name, type):
+    return type.split('/')[-1].split("_")[0]
+
+def main():
+    cell_fuzzers.build_and_add(["../../../resource/picorv32_large.v", "../../../resource/picorv32_large_blockram.v", "../../../resource/distributed_ram.v"], density="7000", family="MachXO2", inc_cell=include_cell_XO2, rw_cell_func=rewrite_celltype_XO2)
+
+
+if __name__ == "__main__":
+    main()

timing/fuzzers/MachXO2/012-io/fuzzer.py

@@ -0,0 +1,29 @@
+import cell_fuzzers
+
+
+def include_cell(name, type):
+    return name.startswith("io_")
+
+
+def rewrite_cell(name, type):
+    if type.startswith("io_"):
+        return "PIO:IOTYPE={}".format(type.split("_", 1)[1])
+    else:
+        return type
+
+
+def rewrite_pin(name, celltype, pin):
+    if type(pin) is list:
+        return list(rewrite_pin(name, celltype, x) for x in pin)
+    if pin.startswith("io_"):
+        return "PAD"
+    else:
+        return pin
+
+
+def main():
+    cell_fuzzers.build_and_add(["pio.v"], inc_cell=include_cell, rw_cell_func=rewrite_cell, rw_pin_func=rewrite_pin, density="7000", family="MachXO2")
+
+
+if __name__ == "__main__":
+    main()

timing/fuzzers/MachXO2/012-io/pio.v

@@ -0,0 +1,49 @@
+module top(
+    input ignore_t,
+    input ignore_i,
+    output [11:0] ignore_o,
+(* IO_TYPE="LVCMOS33" *) inout io_LVCMOS33,
+(* IO_TYPE="LVCMOS25" *) inout io_LVCMOS25,
+(* IO_TYPE="LVCMOS18" *) inout io_LVCMOS18,
+(* IO_TYPE="LVCMOS15" *) inout io_LVCMOS15,
+(* IO_TYPE="LVCMOS12" *) inout io_LVCMOS12,
+
+(* IO_TYPE="LVDS" *) inout io_LVDS,
+(* IO_TYPE="SSTL18_I" *) inout io_SSTL18_I,
+(* IO_TYPE="SSTL18_II" *) inout io_SSTL18_II,
+(* IO_TYPE="SSTL15_I" *) inout io_SSTL15_I,
+(* IO_TYPE="SSTL15_II" *) inout io_SSTL15_II
+
+);
+
+    assign io_LVCMOS33 = ignore_t ? 1'bz : ignore_i;
+    assign ignore_o[0] = io_LVCMOS33;
+
+    assign io_LVCMOS25 = ignore_t ? 1'bz : ignore_i;
+    assign ignore_o[1] = io_LVCMOS25;
+
+    assign io_LVCMOS18 = ignore_t ? 1'bz : ignore_i;
+    assign ignore_o[2] = io_LVCMOS18;
+
+    assign io_LVCMOS15 = ignore_t ? 1'bz : ignore_i;
+    assign ignore_o[3] = io_LVCMOS15;
+
+    assign io_LVCMOS12 = ignore_t ? 1'bz : ignore_i;
+    assign ignore_o[4] = io_LVCMOS12;
+
+    assign io_LVDS = ignore_t ? 1'bz : ignore_i;
+    assign ignore_o[5] = io_LVDS;
+
+    assign io_SSTL18_I = ignore_t ? 1'bz : ignore_i;
+    assign ignore_o[6] = io_SSTL18_I;
+
+    assign io_SSTL18_II = ignore_t ? 1'bz : ignore_i;
+    assign ignore_o[7] = io_SSTL18_II;
+
+    assign io_SSTL15_I = ignore_t ? 1'bz : ignore_i;
+    assign ignore_o[8] = io_SSTL15_I;
+
+    assign io_SSTL15_II = ignore_t ? 1'bz : ignore_i;
+    assign ignore_o[9] = io_SSTL15_II;
+
+endmodule

timing/fuzzers/MachXO2/014-ebr/ebr_regmode.v

@@ -0,0 +1,70 @@
+module top(
+    input [1:0] sel,
+    input [17:0] DIA, DIB,
+    output [17:0] DOA, DOB,
+    input [13:0] ADA, ADB,
+    input CEA, OCEA, CLKA, WEA, CSA2, CSA1, CSA0, RSTA,
+    input CEB, OCEB, CLKB, WEB, CSB2, CSB1, CSB0, RSTB
+);
+
+wire [17:0] DOA_I[0:3];
+wire [17:0] DOB_I[0:3];
+
+DP8KC  #(
+    .REGMODE_A("NOREG"), .REGMODE_B("NOREG")
+) ebr_NOREG_NOREG (
+    .DIA0(DIA[0]), .DIA1(DIA[1]), .DIA2(DIA[2]), .DIA3(DIA[3]), .DIA4(DIA[4]), .DIA5(DIA[5]), .DIA6(DIA[6]), .DIA7(DIA[7]), .DIA8(DIA[8]),
+    .DIB0(DIB[0]), .DIB1(DIB[1]), .DIB2(DIB[2]), .DIB3(DIB[3]), .DIB4(DIB[4]), .DIB5(DIB[5]), .DIB6(DIB[6]), .DIB7(DIB[7]), .DIB8(DIB[8]),
+    .ADA0(ADA[0]), .ADA1(ADA[1]), .ADA2(ADA[2]), .ADA3(ADA[3]), .ADA4(ADA[4]), .ADA5(ADA[5]), .ADA6(ADA[6]), .ADA7(ADA[7]), .ADA8(ADA[8]), .ADA9(ADA[9]), .ADA10(ADA[10]), .ADA11(ADA[11]), .ADA12(ADA[12]),
+    .ADB0(ADB[0]), .ADB1(ADB[1]), .ADB2(ADB[2]), .ADB3(ADB[3]), .ADB4(ADB[4]), .ADB5(ADB[5]), .ADB6(ADB[6]), .ADB7(ADB[7]), .ADB8(ADB[8]), .ADB9(ADB[9]), .ADB10(ADB[10]), .ADB11(ADB[11]), .ADB12(ADB[12]),
+    .DOA0(DOA_I[0][0]), .DOA1(DOA_I[0][1]), .DOA2(DOA_I[0][2]), .DOA3(DOA_I[0][3]), .DOA4(DOA_I[0][4]), .DOA5(DOA_I[0][5]), .DOA6(DOA_I[0][6]), .DOA7(DOA_I[0][7]), .DOA8(DOA_I[0][8]),
+    .DOB0(DOB_I[0][0]), .DOB1(DOB_I[0][1]), .DOB2(DOB_I[0][2]), .DOB3(DOB_I[0][3]), .DOB4(DOB_I[0][4]), .DOB5(DOB_I[0][5]), .DOB6(DOB_I[0][6]), .DOB7(DOB_I[0][7]), .DOB8(DOB_I[0][8]),
+    .CEA(CEA), .OCEA(OCEA), .CLKA(CLKA), .WEA(WEA), .CSA2(CSA2), .CSA1(CSA1), .CSA0(CSA0), .RSTA(RSTA),
+    .CEB(CEB), .OCEB(OCEB), .CLKB(CLKB), .WEB(WEB), .CSB2(CSB2), .CSB1(CSB1), .CSB0(CSB0), .RSTB(RSTB)
+);
+
+DP8KC  #(
+    .REGMODE_A("NOREG"), .REGMODE_B("OUTREG")
+) ebr_NOREG_OUTREG (
+    .DIA0(DIA[0]), .DIA1(DIA[1]), .DIA2(DIA[2]), .DIA3(DIA[3]), .DIA4(DIA[4]), .DIA5(DIA[5]), .DIA6(DIA[6]), .DIA7(DIA[7]), .DIA8(DIA[8]),
+    .DIB0(DIB[0]), .DIB1(DIB[1]), .DIB2(DIB[2]), .DIB3(DIB[3]), .DIB4(DIB[4]), .DIB5(DIB[5]), .DIB6(DIB[6]), .DIB7(DIB[7]), .DIB8(DIB[8]),
+    .ADA0(ADA[0]), .ADA1(ADA[1]), .ADA2(ADA[2]), .ADA3(ADA[3]), .ADA4(ADA[4]), .ADA5(ADA[5]), .ADA6(ADA[6]), .ADA7(ADA[7]), .ADA8(ADA[8]), .ADA9(ADA[9]), .ADA10(ADA[10]), .ADA11(ADA[11]), .ADA12(ADA[12]),
+    .ADB0(ADB[0]), .ADB1(ADB[1]), .ADB2(ADB[2]), .ADB3(ADB[3]), .ADB4(ADB[4]), .ADB5(ADB[5]), .ADB6(ADB[6]), .ADB7(ADB[7]), .ADB8(ADB[8]), .ADB9(ADB[9]), .ADB10(ADB[10]), .ADB11(ADB[11]), .ADB12(ADB[12]),
+    .DOA0(DOA_I[1][0]), .DOA1(DOA_I[1][1]), .DOA2(DOA_I[1][2]), .DOA3(DOA_I[1][3]), .DOA4(DOA_I[1][4]), .DOA5(DOA_I[1][5]), .DOA6(DOA_I[1][6]), .DOA7(DOA_I[1][7]), .DOA8(DOA_I[1][8]),
+    .DOB0(DOB_I[1][0]), .DOB1(DOB_I[1][1]), .DOB2(DOB_I[1][2]), .DOB3(DOB_I[1][3]), .DOB4(DOB_I[1][4]), .DOB5(DOB_I[1][5]), .DOB6(DOB_I[1][6]), .DOB7(DOB_I[1][7]), .DOB8(DOB_I[1][8]),
+    .CEA(CEA), .OCEA(OCEA), .CLKA(CLKA), .WEA(WEA), .CSA2(CSA2), .CSA1(CSA1), .CSA0(CSA0), .RSTA(RSTA),
+    .CEB(CEB), .OCEB(OCEB), .CLKB(CLKB), .WEB(WEB), .CSB2(CSB2), .CSB1(CSB1), .CSB0(CSB0), .RSTB(RSTB)
+);
+
+DP8KC  #(
+    .REGMODE_A("OUTREG"), .REGMODE_B("NOREG")
+) ebr_OUTREG_NOREG (
+    .DIA0(DIA[0]), .DIA1(DIA[1]), .DIA2(DIA[2]), .DIA3(DIA[3]), .DIA4(DIA[4]), .DIA5(DIA[5]), .DIA6(DIA[6]), .DIA7(DIA[7]), .DIA8(DIA[8]),
+    .DIB0(DIB[0]), .DIB1(DIB[1]), .DIB2(DIB[2]), .DIB3(DIB[3]), .DIB4(DIB[4]), .DIB5(DIB[5]), .DIB6(DIB[6]), .DIB7(DIB[7]), .DIB8(DIB[8]),
+    .ADA0(ADA[0]), .ADA1(ADA[1]), .ADA2(ADA[2]), .ADA3(ADA[3]), .ADA4(ADA[4]), .ADA5(ADA[5]), .ADA6(ADA[6]), .ADA7(ADA[7]), .ADA8(ADA[8]), .ADA9(ADA[9]), .ADA10(ADA[10]), .ADA11(ADA[11]), .ADA12(ADA[12]),
+    .ADB0(ADB[0]), .ADB1(ADB[1]), .ADB2(ADB[2]), .ADB3(ADB[3]), .ADB4(ADB[4]), .ADB5(ADB[5]), .ADB6(ADB[6]), .ADB7(ADB[7]), .ADB8(ADB[8]), .ADB9(ADB[9]), .ADB10(ADB[10]), .ADB11(ADB[11]), .ADB12(ADB[12]),
+    .DOA0(DOA_I[2][0]), .DOA1(DOA_I[2][1]), .DOA2(DOA_I[2][2]), .DOA3(DOA_I[2][3]), .DOA4(DOA_I[2][4]), .DOA5(DOA_I[2][5]), .DOA6(DOA_I[2][6]), .DOA7(DOA_I[2][7]), .DOA8(DOA_I[2][8]),
+    .DOB0(DOB_I[2][0]), .DOB1(DOB_I[2][1]), .DOB2(DOB_I[2][2]), .DOB3(DOB_I[2][3]), .DOB4(DOB_I[2][4]), .DOB5(DOB_I[2][5]), .DOB6(DOB_I[2][6]), .DOB7(DOB_I[2][7]), .DOB8(DOB_I[2][8]),
+    .CEA(CEA), .OCEA(OCEA), .CLKA(CLKA), .WEA(WEA), .CSA2(CSA2), .CSA1(CSA1), .CSA0(CSA0), .RSTA(RSTA),
+    .CEB(CEB), .OCEB(OCEB), .CLKB(CLKB), .WEB(WEB), .CSB2(CSB2), .CSB1(CSB1), .CSB0(CSB0), .RSTB(RSTB)
+);
+
+
+DP8KC  #(
+    .REGMODE_A("OUTREG"), .REGMODE_B("OUTREG")
+) ebr_OUTREG_OUTREG (
+    .DIA0(DIA[0]), .DIA1(DIA[1]), .DIA2(DIA[2]), .DIA3(DIA[3]), .DIA4(DIA[4]), .DIA5(DIA[5]), .DIA6(DIA[6]), .DIA7(DIA[7]), .DIA8(DIA[8]),
+    .DIB0(DIB[0]), .DIB1(DIB[1]), .DIB2(DIB[2]), .DIB3(DIB[3]), .DIB4(DIB[4]), .DIB5(DIB[5]), .DIB6(DIB[6]), .DIB7(DIB[7]), .DIB8(DIB[8]),
+    .ADA0(ADA[0]), .ADA1(ADA[1]), .ADA2(ADA[2]), .ADA3(ADA[3]), .ADA4(ADA[4]), .ADA5(ADA[5]), .ADA6(ADA[6]), .ADA7(ADA[7]), .ADA8(ADA[8]), .ADA9(ADA[9]), .ADA10(ADA[10]), .ADA11(ADA[11]), .ADA12(ADA[12]),
+    .ADB0(ADB[0]), .ADB1(ADB[1]), .ADB2(ADB[2]), .ADB3(ADB[3]), .ADB4(ADB[4]), .ADB5(ADB[5]), .ADB6(ADB[6]), .ADB7(ADB[7]), .ADB8(ADB[8]), .ADB9(ADB[9]), .ADB10(ADB[10]), .ADB11(ADB[11]), .ADB12(ADB[12]),
+    .DOA0(DOA_I[3][0]), .DOA1(DOA_I[3][1]), .DOA2(DOA_I[3][2]), .DOA3(DOA_I[3][3]), .DOA4(DOA_I[3][4]), .DOA5(DOA_I[3][5]), .DOA6(DOA_I[3][6]), .DOA7(DOA_I[3][7]), .DOA8(DOA_I[3][8]),
+    .DOB0(DOB_I[3][0]), .DOB1(DOB_I[3][1]), .DOB2(DOB_I[3][2]), .DOB3(DOB_I[3][3]), .DOB4(DOB_I[3][4]), .DOB5(DOB_I[3][5]), .DOB6(DOB_I[3][6]), .DOB7(DOB_I[3][7]), .DOB8(DOB_I[3][8]),
+    .CEA(CEA), .OCEA(OCEA), .CLKA(CLKA), .WEA(WEA), .CSA2(CSA2), .CSA1(CSA1), .CSA0(CSA0), .RSTA(RSTA),
+    .CEB(CEB), .OCEB(OCEB), .CLKB(CLKB), .WEB(WEB), .CSB2(CSB2), .CSB1(CSB1), .CSB0(CSB0), .RSTB(RSTB)
+);
+
+assign DOA = DOA_I[sel];
+assign DOB = DOB_I[sel];
+
+
+endmodule

timing/fuzzers/MachXO2/014-ebr/ebr_writemode.v

@@ -0,0 +1,59 @@
+module top(
+    input [1:0] sel,
+    input [17:0] DIA, DIB,
+    output [17:0] DOA, DOB,
+    input [13:0] ADA, ADB,
+    input CEA, OCEA, CLKA, WEA, CSA2, CSA1, CSA0, RSTA,
+    input CEB, OCEB, CLKB, WEB, CSB2, CSB1, CSB0, RSTB
+);
+
+wire [17:0] DOA_I[0:2];
+wire [17:0] DOB_I[0:2];
+
+DP8KC  #(
+    .WRITEMODE_A("NORMAL"), .WRITEMODE_B("NORMAL")
+) ebr_NORMAL_NORMAL (
+    .DIA0(DIA[0]), .DIA1(DIA[1]), .DIA2(DIA[2]), .DIA3(DIA[3]), .DIA4(DIA[4]), .DIA5(DIA[5]), .DIA6(DIA[6]), .DIA7(DIA[7]), .DIA8(DIA[8]),
+    .DIB0(DIB[0]), .DIB1(DIB[1]), .DIB2(DIB[2]), .DIB3(DIB[3]), .DIB4(DIB[4]), .DIB5(DIB[5]), .DIB6(DIB[6]), .DIB7(DIB[7]), .DIB8(DIB[8]),
+    .ADA0(ADA[0]), .ADA1(ADA[1]), .ADA2(ADA[2]), .ADA3(ADA[3]), .ADA4(ADA[4]), .ADA5(ADA[5]), .ADA6(ADA[6]), .ADA7(ADA[7]), .ADA8(ADA[8]), .ADA9(ADA[9]), .ADA10(ADA[10]), .ADA11(ADA[11]), .ADA12(ADA[12]),
+    .ADB0(ADB[0]), .ADB1(ADB[1]), .ADB2(ADB[2]), .ADB3(ADB[3]), .ADB4(ADB[4]), .ADB5(ADB[5]), .ADB6(ADB[6]), .ADB7(ADB[7]), .ADB8(ADB[8]), .ADB9(ADB[9]), .ADB10(ADB[10]), .ADB11(ADB[11]), .ADB12(ADB[12]),
+    .DOA0(DOA_I[0][0]), .DOA1(DOA_I[0][1]), .DOA2(DOA_I[0][2]), .DOA3(DOA_I[0][3]), .DOA4(DOA_I[0][4]), .DOA5(DOA_I[0][5]), .DOA6(DOA_I[0][6]), .DOA7(DOA_I[0][7]), .DOA8(DOA_I[0][8]),
+    .DOB0(DOB_I[0][0]), .DOB1(DOB_I[0][1]), .DOB2(DOB_I[0][2]), .DOB3(DOB_I[0][3]), .DOB4(DOB_I[0][4]), .DOB5(DOB_I[0][5]), .DOB6(DOB_I[0][6]), .DOB7(DOB_I[0][7]), .DOB8(DOB_I[0][8]),
+    .CEA(CEA), .OCEA(OCEA), .CLKA(CLKA), .WEA(WEA), .CSA2(CSA2), .CSA1(CSA1), .CSA0(CSA0), .RSTA(RSTA),
+    .CEB(CEB), .OCEB(OCEB), .CLKB(CLKB), .WEB(WEB), .CSB2(CSB2), .CSB1(CSB1), .CSB0(CSB0), .RSTB(RSTB)
+);
+
+DP8KC  #(
+    .WRITEMODE_A("NORMAL"), .WRITEMODE_B("READBEFOREWRITE")
+) ebr_NORMAL_READBEFOREWRITE (
+    .DIA0(DIA[0]), .DIA1(DIA[1]), .DIA2(DIA[2]), .DIA3(DIA[3]), .DIA4(DIA[4]), .DIA5(DIA[5]), .DIA6(DIA[6]), .DIA7(DIA[7]), .DIA8(DIA[8]),
+    .DIB0(DIB[0]), .DIB1(DIB[1]), .DIB2(DIB[2]), .DIB3(DIB[3]), .DIB4(DIB[4]), .DIB5(DIB[5]), .DIB6(DIB[6]), .DIB7(DIB[7]), .DIB8(DIB[8]),
+    .ADA0(ADA[0]), .ADA1(ADA[1]), .ADA2(ADA[2]), .ADA3(ADA[3]), .ADA4(ADA[4]), .ADA5(ADA[5]), .ADA6(ADA[6]), .ADA7(ADA[7]), .ADA8(ADA[8]), .ADA9(ADA[9]), .ADA10(ADA[10]), .ADA11(ADA[11]), .ADA12(ADA[12]),
+    .ADB0(ADB[0]), .ADB1(ADB[1]), .ADB2(ADB[2]), .ADB3(ADB[3]), .ADB4(ADB[4]), .ADB5(ADB[5]), .ADB6(ADB[6]), .ADB7(ADB[7]), .ADB8(ADB[8]), .ADB9(ADB[9]), .ADB10(ADB[10]), .ADB11(ADB[11]), .ADB12(ADB[12]),
+    .DOA0(DOA_I[1][0]), .DOA1(DOA_I[1][1]), .DOA2(DOA_I[1][2]), .DOA3(DOA_I[1][3]), .DOA4(DOA_I[1][4]), .DOA5(DOA_I[1][5]), .DOA6(DOA_I[1][6]), .DOA7(DOA_I[1][7]), .DOA8(DOA_I[1][8]),
+    .DOB0(DOB_I[1][0]), .DOB1(DOB_I[1][1]), .DOB2(DOB_I[1][2]), .DOB3(DOB_I[1][3]), .DOB4(DOB_I[1][4]), .DOB5(DOB_I[1][5]), .DOB6(DOB_I[1][6]), .DOB7(DOB_I[1][7]), .DOB8(DOB_I[1][8]),
+    .CEA(CEA), .OCEA(OCEA), .CLKA(CLKA), .WEA(WEA), .CSA2(CSA2), .CSA1(CSA1), .CSA0(CSA0), .RSTA(RSTA),
+    .CEB(CEB), .OCEB(OCEB), .CLKB(CLKB), .WEB(WEB), .CSB2(CSB2), .CSB1(CSB1), .CSB0(CSB0), .RSTB(RSTB)
+);
+
+DP8KC  #(
+   .WRITEMODE_A("NORMAL"), .WRITEMODE_B("WRITETHROUGH")
+) ebr_NORMAL_WRITETHROUGH (
+    .DIA0(DIA[0]), .DIA1(DIA[1]), .DIA2(DIA[2]), .DIA3(DIA[3]), .DIA4(DIA[4]), .DIA5(DIA[5]), .DIA6(DIA[6]), .DIA7(DIA[7]), .DIA8(DIA[8]),
+    .DIB0(DIB[0]), .DIB1(DIB[1]), .DIB2(DIB[2]), .DIB3(DIB[3]), .DIB4(DIB[4]), .DIB5(DIB[5]), .DIB6(DIB[6]), .DIB7(DIB[7]), .DIB8(DIB[8]),
+    .ADA0(ADA[0]), .ADA1(ADA[1]), .ADA2(ADA[2]), .ADA3(ADA[3]), .ADA4(ADA[4]), .ADA5(ADA[5]), .ADA6(ADA[6]), .ADA7(ADA[7]), .ADA8(ADA[8]), .ADA9(ADA[9]), .ADA10(ADA[10]), .ADA11(ADA[11]), .ADA12(ADA[12]),
+    .ADB0(ADB[0]), .ADB1(ADB[1]), .ADB2(ADB[2]), .ADB3(ADB[3]), .ADB4(ADB[4]), .ADB5(ADB[5]), .ADB6(ADB[6]), .ADB7(ADB[7]), .ADB8(ADB[8]), .ADB9(ADB[9]), .ADB10(ADB[10]), .ADB11(ADB[11]), .ADB12(ADB[12]),
+    .DOA0(DOA_I[2][0]), .DOA1(DOA_I[2][1]), .DOA2(DOA_I[2][2]), .DOA3(DOA_I[2][3]), .DOA4(DOA_I[2][4]), .DOA5(DOA_I[2][5]), .DOA6(DOA_I[2][6]), .DOA7(DOA_I[2][7]), .DOA8(DOA_I[2][8]),
+    .DOB0(DOB_I[2][0]), .DOB1(DOB_I[2][1]), .DOB2(DOB_I[2][2]), .DOB3(DOB_I[2][3]), .DOB4(DOB_I[2][4]), .DOB5(DOB_I[2][5]), .DOB6(DOB_I[2][6]), .DOB7(DOB_I[2][7]), .DOB8(DOB_I[2][8]),
+    .CEA(CEA), .OCEA(OCEA), .CLKA(CLKA), .WEA(WEA), .CSA2(CSA2), .CSA1(CSA1), .CSA0(CSA0), .RSTA(RSTA),
+    .CEB(CEB), .OCEB(OCEB), .CLKB(CLKB), .WEB(WEB), .CSB2(CSB2), .CSB1(CSB1), .CSB0(CSB0), .RSTB(RSTB)
+);
+
+
+
+
+assign DOA = DOA_I[sel];
+assign DOB = DOB_I[sel];
+
+
+endmodule

timing/fuzzers/MachXO2/014-ebr/fuzzer.py

@@ -0,0 +1,27 @@
+import cell_fuzzers
+
+
+def include_cell(name, type):
+    return name.startswith("ebr_")
+
+
+def rewrite_cell_regmode(name, type):
+    if type.startswith("ebr_"):
+        return "DP8KC:REGMODE_A={},REGMODE_B={}".format(type.split("_", 2)[1], type.split("_", 2)[2])
+    else:
+        return type
+
+def rewrite_cell_wrmode(name, type):
+    if type.startswith("ebr_"):
+        return "DP8KC:WRITEMODE_A={},WRITEMODE_B={}".format(type.split("_", 2)[1], type.split("_", 2)[2])
+    else:
+        return type
+
+
+def main():
+    cell_fuzzers.build_and_add(["ebr_regmode.v"], inc_cell=include_cell, rw_cell_func=rewrite_cell_regmode, density="7000", family="MachXO2")
+    cell_fuzzers.build_and_add(["ebr_writemode.v"], inc_cell=include_cell, rw_cell_func=rewrite_cell_wrmode, density="7000", family="MachXO2")
+
+
+if __name__ == "__main__":
+    main()

timing/fuzzers/MachXO2/020-basic_routing/fuzzer.py

@@ -0,0 +1,27 @@
+import timing_solver
+import timing_dbs
+import cell_fuzzers
+import json
+import fuzzloops
+
+
+def main():
+    jobs = []
+    jobs += cell_fuzzers.timing_configs("picorv32", "../../../resource/picorv32_large.v", density="7000", family="MachXO2")
+
+    def per_job(job):
+        grade, cfg = job
+        cfg.setup(skip_specimen=True)
+        bitf = cfg.build_design(cfg.ncl, {}, backanno=True, substitute=False)
+        ncl = bitf.replace(".bit", "_out.ncl")
+        sdf = bitf.replace(".bit", ".sdf")
+        data = timing_solver.solve_pip_delays(ncl, sdf)
+        db = timing_dbs.interconnect_db_path("MachXO2", grade)
+        with open(db, "w") as f:
+            json.dump(data, f, indent=4, sort_keys=True)
+
+    fuzzloops.parallel_foreach(jobs, per_job)
+
+
+if __name__ == "__main__":
+    main()

timing/fuzzers/MachXO3D/010-basic-cells/fuzzer.py

@@ -0,0 +1,16 @@
+import cell_fuzzers
+
+def include_cell_XO3D(name, type):
+    type = type.split('/')[-1].split("_")[0]
+    return type.isupper() and "_" not in type
+
+
+def rewrite_celltype_XO3D(name, type):
+    return type.split('/')[-1].split("_")[0]
+
+def main():
+    cell_fuzzers.build_and_add(["../../../resource/picorv32_large.v", "../../../resource/picorv32_large_blockram.v", "../../../resource/distributed_ram.v"], density="9400", family="MachXO3D", inc_cell=include_cell_XO3D, rw_cell_func=rewrite_celltype_XO3D)
+
+
+if __name__ == "__main__":
+    main()

timing/fuzzers/MachXO3D/012-io/fuzzer.py

@@ -0,0 +1,29 @@
+import cell_fuzzers
+
+
+def include_cell(name, type):
+    return name.startswith("io_")
+
+
+def rewrite_cell(name, type):
+    if type.startswith("io_"):
+        return "PIO:IOTYPE={}".format(type.split("_", 1)[1])
+    else:
+        return type
+
+
+def rewrite_pin(name, celltype, pin):
+    if type(pin) is list:
+        return list(rewrite_pin(name, celltype, x) for x in pin)
+    if pin.startswith("io_"):
+        return "PAD"
+    else:
+        return pin
+
+
+def main():
+    cell_fuzzers.build_and_add(["pio.v"], inc_cell=include_cell, rw_cell_func=rewrite_cell, rw_pin_func=rewrite_pin, density="9400", family="MachXO3D")
+
+
+if __name__ == "__main__":
+    main()

timing/fuzzers/MachXO3D/012-io/pio.v

@@ -0,0 +1,49 @@
+module top(
+    input ignore_t,
+    input ignore_i,
+    output [11:0] ignore_o,
+(* IO_TYPE="LVCMOS33" *) inout io_LVCMOS33,
+(* IO_TYPE="LVCMOS25" *) inout io_LVCMOS25,
+(* IO_TYPE="LVCMOS18" *) inout io_LVCMOS18,
+(* IO_TYPE="LVCMOS15" *) inout io_LVCMOS15,
+(* IO_TYPE="LVCMOS12" *) inout io_LVCMOS12,
+
+(* IO_TYPE="LVDS" *) inout io_LVDS,
+(* IO_TYPE="LVDS25" *) inout io_LVDS25,
+(* IO_TYPE="LVPECL33" *) inout io_LVPECL33,
+(* IO_TYPE="MIPI" *) inout io_MIPI,
+(* IO_TYPE="LVTTL33" *) inout io_LVTTL33
+
+);
+
+    assign io_LVCMOS33 = ignore_t ? 1'bz : ignore_i;
+    assign ignore_o[0] = io_LVCMOS33;
+
+    assign io_LVCMOS25 = ignore_t ? 1'bz : ignore_i;
+    assign ignore_o[1] = io_LVCMOS25;
+
+    assign io_LVCMOS18 = ignore_t ? 1'bz : ignore_i;
+    assign ignore_o[2] = io_LVCMOS18;
+
+    assign io_LVCMOS15 = ignore_t ? 1'bz : ignore_i;
+    assign ignore_o[3] = io_LVCMOS15;
+
+    assign io_LVCMOS12 = ignore_t ? 1'bz : ignore_i;
+    assign ignore_o[4] = io_LVCMOS12;
+
+    assign io_LVDS = ignore_t ? 1'bz : ignore_i;
+    assign ignore_o[5] = io_LVDS;
+
+    assign io_LVDS25 = ignore_t ? 1'bz : ignore_i;
+    assign ignore_o[6] = io_LVDS25;
+
+    assign io_LVPECL33 = ignore_t ? 1'bz : ignore_i;
+    assign ignore_o[7] = io_LVPECL33;
+
+    assign io_MIPI = ignore_t ? 1'bz : ignore_i;
+    assign ignore_o[8] = io_MIPI;
+
+    assign io_LVTTL33 = ignore_t ? 1'bz : ignore_i;
+    assign ignore_o[9] = io_LVTTL33;
+
+endmodule