[proposal][wip] Add event trace configuration to mlir-aie

include/aie/Dialect/AIE/IR/AIEAttrs.td

@@ -12,6 +12,7 @@
 #define AIE_ATTRS
 
 include "aie/Dialect/AIE/IR/AIE.td"
+include "aie/Dialect/AIE/IR/AIETraceAttrs.td"
 
 include "mlir/IR/AttrTypeBase.td"
 include "mlir/IR/EnumAttr.td"
@@ -206,5 +207,12 @@
 def InitValuesArrayAttr
   : OptionalAttr<TypedArrayAttrBase<ElementsAttr, "array of ElementsAttr">>;
 
+//===----------------------------------------------------------------------===//
+// Generated AIE event enumerations
+//===----------------------------------------------------------------------===//
+
+include "aie/Dialect/AIE/IR/AIEEventsAIE.td.inc"
+include "aie/Dialect/AIE/IR/AIEEventsAIE2.td.inc"
+include "aie/Dialect/AIE/IR/AIEEventsAIE2P.td.inc"
 
 #endif // AIE_ATTRS

include/aie/Dialect/AIE/IR/AIEDialect.h

@@ -195,6 +195,11 @@ void printObjectFifoConsumerTiles(mlir::OpAsmPrinter &printer,
 
 int32_t getBufferBaseAddress(mlir::Operation *bufOp);
 
+// Trace Event Value Parsing/Printing (handles both string and typed enums)
+mlir::ParseResult parseTraceEvent(mlir::AsmParser &parser,
+                                  mlir::Attribute &result);
+void printTraceEventEnum(mlir::AsmPrinter &printer, mlir::Attribute attr);
+
 } // namespace xilinx::AIE
 
 // include TableGen generated Op definitions

include/aie/Dialect/AIE/IR/AIEOps.td

@@ -27,6 +27,8 @@ include "mlir/Interfaces/SideEffectInterfaces.td"
 class AIE_Op<string mnemonic, list<Trait> traits = []> :
     Op<AIE_Dialect, mnemonic, traits>;
 
+include "aie/Dialect/AIE/IR/AIETraceOps.td"
+
 
 def AIE_DeviceOp: AIE_Op<"device", [
     Symbol,

include/aie/Dialect/AIE/IR/AIERegisterDatabase.h

@@ -0,0 +1,117 @@
+//===- AIERegisterDatabase.h ------------------------------------*- C++ -*-===//
+//
+// This file is licensed under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+// Copyright (C) 2025, Advanced Micro Devices, Inc.
+//
+//===----------------------------------------------------------------------===//
+// Register and event database for AIE trace configuration
+//===----------------------------------------------------------------------===//
+
+#ifndef AIE_REGISTER_DATABASE_H
+#define AIE_REGISTER_DATABASE_H
+
+#include "llvm/ADT/StringMap.h"
+#include "llvm/ADT/StringRef.h"
+#include "llvm/Support/JSON.h"
+#include <optional>
+#include <string>
+#include <vector>
+
+namespace mlir {
+class Operation;
+}
+
+namespace xilinx {
+namespace AIE {
+
+class TileOp;
+
+/// Bit field information for a register
+struct BitFieldInfo {
+  std::string name;
+  uint32_t bit_start; // LSB position
+  uint32_t bit_end;   // MSB position
+  std::string type;
+  std::string reset;
+  std::string description;
+
+  uint32_t getWidth() const { return bit_end - bit_start + 1; }
+};
+
+/// Register information
+struct RegisterInfo {
+  std::string name;
+  uint32_t offset;
+  std::string module;
+  uint32_t width;
+  std::string type;
+  std::string reset;
+  std::string description;
+  std::vector<BitFieldInfo> bit_fields;
+
+  const BitFieldInfo *getField(llvm::StringRef fieldName) const;
+};
+
+/// Event information
+struct EventInfo {
+  std::string name;
+  uint32_t number;
+  std::string module; // core, memory, pl, mem_tile
+};
+
+/// Register and event database for a specific architecture
+class RegisterDatabase {
+public:
+  /// Load database for AIE2 architecture
+  static std::unique_ptr<RegisterDatabase> loadAIE2();
+
+  /// Lookup register by name and module
+  const RegisterInfo *lookupRegister(llvm::StringRef name,
+                                     llvm::StringRef module) const;
+
+  /// Lookup register by name, determining module from tile
+  const RegisterInfo *lookupRegister(llvm::StringRef name, TileOp tile,
+                                     bool isMem = false) const;
+
+  /// Lookup event by name and module
+  std::optional<uint32_t> lookupEvent(llvm::StringRef name,
+                                      llvm::StringRef module) const;
+
+  /// Lookup event by name, determining module from tile
+  std::optional<uint32_t> lookupEvent(llvm::StringRef name, TileOp tile,
+                                      bool isMem = false) const;
+
+  /// Encode a value for a specific bitfield
+  uint32_t encodeFieldValue(const BitFieldInfo &field, uint32_t value) const;
+
+  /// Resolve "PORT:CHANNEL" value to stream switch port index
+  /// @param value String in format "PORT:CHANNEL" (e.g., "NORTH:1", "DMA:0")
+  /// @param tile Tile operation (for context)
+  /// @param master True for master port, false for slave
+  /// @return Port index, or nullopt if invalid/unsupported
+  std::optional<uint32_t> resolvePortValue(llvm::StringRef value, TileOp tile,
+                                           bool master) const;
+
+  /// Get register module name for a tile (CORE_MODULE, PL_MODULE, etc.)
+  static llvm::StringRef getRegisterModuleForTile(TileOp tile,
+                                                  bool isMem = false);
+
+  /// Get event module name for a tile (core, pl, memory, etc.)
+  static llvm::StringRef getEventModuleForTile(TileOp tile, bool isMem = false);
+
+private:
+  RegisterDatabase() = default;
+
+  bool loadFromJSON(llvm::StringRef registerPath, llvm::StringRef eventPath);
+
+  llvm::StringMap<RegisterInfo> registers_;
+  llvm::StringMap<EventInfo> events_;
+};
+
+} // namespace AIE
+} // namespace xilinx
+
+#endif // AIE_REGISTER_DATABASE_H

include/aie/Dialect/AIE/IR/AIETargetModel.h

@@ -12,13 +12,18 @@
 #define MLIR_AIE_DEVICEMODEL_H
 
 #include "aie/Dialect/AIE/IR/AIEEnums.h"
+#include "aie/Dialect/AIE/IR/AIERegisterDatabase.h"
 
 #include "llvm/ADT/DenseSet.h"
 
 #include <iostream>
+#include <memory>
 
 namespace xilinx::AIE {
 
+// Forward declarations
+class TileOp;
+
 using TileID = struct TileID {
   // friend definition (will define the function as a non-member function in the
   // namespace surrounding the class).
@@ -97,6 +102,20 @@ class AIETargetModel {
 
   uint32_t ModelProperties = 0;
 
+  // Register database (loaded lazily on first access)
+  mutable std::unique_ptr<RegisterDatabase> regDB;
+  mutable bool regDBLoadAttempted = false;
+
+protected:
+  /// Subclasses override to provide architecture-specific database loading.
+  /// Returns nullptr if register database is not available for this
+  /// architecture.
+  virtual std::unique_ptr<RegisterDatabase> loadRegisterDatabase() const;
+
+  /// Get the register database, loading it lazily on first access.
+  /// Throws fatal error if database is required but unavailable.
+  const RegisterDatabase *getRegisterDatabase() const;
+
 public:
   TargetModelKind getKind() const { return kind; }
 
@@ -240,6 +259,29 @@ class AIETargetModel {
   virtual std::optional<uint32_t> getLocalLockAddress(uint32_t lockId,
                                                       TileID tile) const = 0;
 
+  /// Get stream switch port index for a given port specification
+  /// @param col Tile column
+  /// @param row Tile row
+  /// @param bundle Port type (WireBundle enum: DMA, FIFO, North, South, East,
+  /// West, Core, etc.)
+  /// @param channel Channel/port number within the bundle
+  /// @param master True for master port, false for slave port
+  /// @return Port index for Stream_Switch_Event_Port_Selection register, or
+  /// nullopt if invalid
+  virtual std::optional<uint32_t>
+  getStreamSwitchPortIndex(int col, int row, WireBundle bundle,
+                           uint32_t channel, bool master) const = 0;
+
+  /// Check if a stream switch port is valid for the given tile
+  /// @param col Tile column
+  /// @param row Tile row
+  /// @param bundle Port type
+  /// @param channel Channel/port number
+  /// @param master Master/slave direction
+  /// @return True if the port configuration is valid
+  virtual bool isValidStreamSwitchPort(int col, int row, WireBundle bundle,
+                                       uint32_t channel, bool master) const = 0;
+
   /// Return the number of buffer descriptors supported by the DMA in the given
   /// tile.
   virtual uint32_t getNumBDs(int col, int row) const = 0;
@@ -325,6 +367,43 @@ class AIETargetModel {
 
   // Returns true if the target model supports the given block format.
   virtual bool isSupportedBlockFormat(std::string const &format) const;
+
+  /// Register Database API - provides access to register and event information
+  /// for trace configuration and low-level register access.
+
+  /// Lookup register information by name and tile.
+  /// @param name Register name (e.g., "Trace_Control0")
+  /// @param tile Tile operation to determine module context
+  /// @param isMem True for memory module registers, false for core/shim
+  /// @return Pointer to register info, or nullptr if not found
+  /// @throws fatal_error if database required but unavailable
+  const RegisterInfo *lookupRegister(llvm::StringRef name, TileOp tile,
+                                     bool isMem = false) const;
+
+  /// Lookup event number by name and tile.
+  /// @param name Event name (e.g., "INSTR_EVENT_0", "DMA_S2MM_0_START_TASK")
+  /// @param tile Tile operation to determine module context
+  /// @param isMem True for memory module events, false for core/shim
+  /// @return Event number if found, nullopt otherwise
+  /// @throws fatal_error if database required but unavailable
+  std::optional<uint32_t> lookupEvent(llvm::StringRef name, TileOp tile,
+                                      bool isMem = false) const;
+
+  /// Encode a field value with proper bit shifting.
+  /// @param field Bit field information
+  /// @param value Value to encode
+  /// @return Value shifted to correct bit position
+  /// @throws fatal_error if database required but unavailable
+  uint32_t encodeFieldValue(const BitFieldInfo &field, uint32_t value) const;
+
+  /// Resolve stream switch port specification to port index.
+  /// @param value Port specification string (e.g., "NORTH:1", "DMA:0")
+  /// @param tile Tile operation for context
+  /// @param master True for master port, false for slave
+  /// @return Port index for stream switch register, or nullopt if invalid
+  /// @throws fatal_error if database required but unavailable
+  std::optional<uint32_t> resolvePortValue(llvm::StringRef value, TileOp tile,
+                                           bool master) const;
 };
 
 class AIE1TargetModel : public AIETargetModel {
@@ -403,6 +482,13 @@ class AIE1TargetModel : public AIETargetModel {
                              int srcChan, WireBundle dstBundle,
                              int dstChan) const override;
 
+  std::optional<uint32_t> getStreamSwitchPortIndex(int col, int row,
+                                                   WireBundle bundle,
+                                                   uint32_t channel,
+                                                   bool master) const override;
+  bool isValidStreamSwitchPort(int col, int row, WireBundle bundle,
+                               uint32_t channel, bool master) const override;
+
   uint32_t getColumnShift() const override { return 23; }
   uint32_t getRowShift() const override { return 18; }
 
@@ -416,6 +502,9 @@ class AIE1TargetModel : public AIETargetModel {
 };
 
 class AIE2TargetModel : public AIETargetModel {
+protected:
+  std::unique_ptr<RegisterDatabase> loadRegisterDatabase() const override;
+
 public:
   AIE2TargetModel(TargetModelKind k) : AIETargetModel(k) {
     // Device properties initialization
@@ -509,6 +598,13 @@ class AIE2TargetModel : public AIETargetModel {
                              int srcChan, WireBundle dstBundle,
                              int dstChan) const override;
 
+  std::optional<uint32_t> getStreamSwitchPortIndex(int col, int row,
+                                                   WireBundle bundle,
+                                                   uint32_t channel,
+                                                   bool master) const override;
+  bool isValidStreamSwitchPort(int col, int row, WireBundle bundle,
+                               uint32_t channel, bool master) const override;
+
   uint32_t getColumnShift() const override { return 25; }
   uint32_t getRowShift() const override { return 20; }