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This patch fixes a bug present in both xllfifo_interrupt_example.c #67

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@shearl shearl commented Nov 7, 2018

and xllfifo_polling_example.c in which false positives can occur
because the test transmit buffer is only filled with zeros.
This patch also fixes a bug in xllfifo_interrupt_example.c in the
receive data function in which it breaks the rule from pg080 which
states: RDFO should be read before reading RLR. Reading RLR first
will result in the RDFO being reset to zero. Without this fix, the
test fails when the transmit buffer is filled with non-zero data.

mubinsyed and others added 30 commits April 3, 2018 18:35
By default CPUACTLR_EL1 is accessible only from EL3,
it results into abort if accessed from EL1 non
secure privilege level.

This patch updates Xil_ConfigureL1Prefetch function
to avoid said issue.

Signed-off-by: Mubin Sayyed <mubinusm@xilinx.com>

Acked-for-series: Radhey Shyam Pandey <radheys@xilinx.com>
Updated hypervisor enabled BSP to use PV console,
based on XEN_USE_PV_CONSOLE flag.

Signed-off-by: Mubin Sayyed <mubinusm@xilinx.com>

Acked-for-series: Radhey Shyam Pandey <radheys@xilinx.com>

Acked-for-series: Radhey Shyam Pandey <radheys@xilinx.com>
Signed-off-by: Eric Bong <nyongnyi@xilinx.com>
Signed-off-by: Eric Bong <nyongnyi@xilinx.com>
Acked-by: Yunhai Qiao <yunhaiq@xilinx.com>

Acked-by: Yunhai Qiao <yunhaiq@xilinx.com>
Signed-off-by: Eric Bong <nyongnyi@xilinx.com>
Acked-by: Yunhai Qiao <yunhaiq@xilinx.com>

Acked-by: Yunhai Qiao <yunhaiq@xilinx.com>
Signed-off-by: Eric Bong <nyongnyi@xilinx.com>
Acked-by: Yunhai Qiao <yunhaiq@xilinx.com>

Acked-by: Yunhai Qiao <yunhaiq@xilinx.com>
This patch is to factor-in the 0.5% refclk deviation and 10KHz clkdet accuracy into the userclk error detection in XVphy_HdmiCpllParam & XVphy_HdmiQpllParam APIs.

Signed-off-by: Gilbert Magnaye <gmagnay@xilinx.com>
Acked-by: Eric Bong <nyongnyi@xilinx.com>

Acked-by: Eric Bong <nyongnyi@xilinx.com>
Update changelog for PL DMA's(dma, cdma, mcdma and vdma)
and axiethernet.

Signed-off-by: Radhey Shyam Pandey <radheys@xilinx.com>
Acked-by: Kedareswara rao Appana <appanad@xilinx.com>

Acked-by: Kedareswara rao Appana <appanad@xilinx.com>
…ion removal in FSBL

This reverts commit bb9020b.

Signed-off-by: Vikram Sreenivasa Batchali <bvikram@xilinx.com>

Acked-by: Srikanth Vemula <svemula@xilinx.com>
Signed-off-by: Mubin Sayyed <mubinusm@xilinx.com>

Acked-by:Ilias Ibrahim <mmo@xilinx.com>
This patch updates the following registers as part of
PLL settings based on the latest IP values.
PLL_LPF1, PLL_CRS2 and PLL_CRS1.

Signed-off-by: Sai Krishna Potthuri <lakshmis@xilinx.com>

Acked-for-series: Srinivas Goud <sgoud@xilinx.com>
Signed-off-by: Anand Ashok Dumbre <anand.ashok.dumbre@xilinx.com>

Acked-by: Satish Kumar Nagireddy <satishna@xilinx.com>
Signed-off-by: Anand Ashok Dumbre <anand.ashok.dumbre@xilinx.com>

Acked-by: Satish Kumar Nagireddy <satishna@xilinx.com>
This patch updates PMU Firmware misc folder with WDT driver information

Signed-off-by: Mounika Grace Akula <makula@xilinx.com>
Acked-by: Will Wong <willw@xilinx.com>
Starting from 2018.1 release, PMU uses IPI-channel 2 for communication
initiated by PMU to other masters. This requires IPI configuration file
to be added to misc folder. This patch updates PMU Firmware misc folder
with ipi configuration file

Signed-off-by: Mounika Grace Akula <makula@xilinx.com>
Acked-by: Sarat Chand Savitala <saratcha@xilinx.com>
add memory video format BGR8

Signed-off-by: Vanessa Chou <vanessay@xilinx.com>
add interlaced support, memory format BGR8, interrupt for ap_ready

Signed-off-by: Vanessa Chou <vanessay@xilinx.com>
Added support for interlaced, memory format BGR8, interrupt for ap_ready

Signed-off-by: Vanessa Chou <vanessay@xilinx.com>
Acked-for-series: Vishal Sagar<vsagar@xilinx.com>
Example design tcl and application code updated to match
changes in HW

Signed-off-by: Vanessa Chou <vanessay@xilinx.com>
Example design tcl and application code updated to match
changes in HW

Signed-off-by: Vanessa Chou <vanessay@xilinx.com>
Example design readme, tcl, and application code
updated to match change in HW

Signed-off-by: Vanessa Chou <vanessay@xilinx.com>
Fix for H Scaler setup when input is 420
Example design tcl and application code updated to match
changes in HW

Signed-off-by: Vanessa Chou <vanessay@xilinx.com>
fix assert in field id
add 8th overlayer
move logo enable bit from 8 to 15
USB drivers code underwent clean up process in 2018.1. This patch updates
FSBL code to be in sync with the updated usb driver code.

Signed-off-by: Vikram Sreenivasa Batchali <bvikram@xilinx.com>

Acked-by: Anurag Kumar Vulisha <anuragku@xilinx.com>
Signed-off-by: Siva Addepalli <saddepal@xilinx.com>
…ble command.

For some parts, it is mandatory to issue write enable before sending
4B Enter/Exit commands. So in dual parallel mode we are not enabling both
CS when issuing write enable command, causing write failures. This patch
fixes this issue.

Signed-off-by: Tejas Prajapati Rameshchandra <tejaspra@xilinx.com>

Acked-for-series: Naga Sureshkumar Relli <nagasure@xilinx.com>
Put Linaro to the license text in the files of libmetal
Zephyr implementation.

Signed-off-by: Wendy Liang <jliang@xilinx.com>
Acked-by: Anirudha Sarangi <anirudh@xilinx.com>

Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
Signed-off-by: Siva Addepalli <saddepal@xilinx.com>
Acked-by: Srikanth Vemula <svemula@xilinx.com>
Signed-off-by: Siva Addepalli <saddepal@xilinx.com>
Acked-by: Srikanth Vemula <svemula@xilinx.com>
Vikram Sreenivasa Batchali and others added 18 commits June 6, 2018 18:07
This is because microzed is not supported by SDK.

Signed-off-by: Vikram Sreenivasa Batchali <bvikram@xilinx.com>
Acked-by: Sarat Chand Savitala <saratcha@xilinx.com>
…er reading from FMC EEPROM

This patch adds code to wait for the I2C bus to become idle after reading from FMC EEPROM.
This is to avoid errors in subsequent I2C operations.

Signed-off-by: Vikram Sreenivasa Batchali <bvikram@xilinx.com>
Acked-by: Krishna Chaitanya Patakamuri <kpataka@xilinx.com>
The existing API has bugs with respect to returning handler
information from the Exception vector table.
The patch fixes this.

Signed-off-by: Anirudha Sarangi <anirudh@xilinx.com>

Acked-for-series: Sai Krishna Potthuri<lakshmis@xilinx.com>
The implementation has bugs the way it gets and restores the
exception handlers in exception vector table.
The patch fixes it.

Signed-off-by: Anirudha Sarangi <anirudh@xilinx.com>

Acked-for-series: Sai Krishna Potthuri<lakshmis@xilinx.com>
Updated PMU Firmware misc folder to remove few harmless warning which
appear while building BSP

Signed-off-by: Mounika Grace Akula <makula@xilinx.com>
Acked-by: Will Wong <willw@xilinx.com>
Add one more frequency to the lmx table.

Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>

Acked-for-series: Sai Krishna Potthuri<lakshmis@xilinx.com>
…f zcu111 boards

Update the lmk clock frequencies for different revisions of zcu111 boards

Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>

Acked-for-series: Sai Krishna Potthuri<lakshmis@xilinx.com>
Spec change on PLL Reference clock lower limit value hence updated
the minimum value supported for reference clock to 102.4062MHz in
XRFdc_DynamicPLLConfig() API.

Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com>

Acked-for-series: Anirudha Sarangi <anirudh@xilinx.com>
Calibration mode is applicable only for ADC hence removed
checking the calibration mode for DAC blocks.

Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com>

Acked-for-series: Anirudha Sarangi <anirudh@xilinx.com>
…4 FSBL

The patch fixes errors related to addressing of and reading from EEPROM.

Signed-off-by: Vikram Sreenivasa Batchali <bvikram@xilinx.com>
…U104

This code removes unwanted PMBUS commands from FSBL ZCU104 board.

Signed-off-by: Vikram Sreenivasa Batchali <bvikram@xilinx.com>
Acked-for-series: Krishna Chaitanya Patakamuri <kpataka@xilinx.com>
This patch fixes compilation warnings

Signed-off-by: Vikram Sreenivasa Batchali <bvikram@xilinx.com>
Acked-by: Sarat Chand Savitala <saratcha@xilinx.com>
This reverts commit 20803400cd262f54ddf6cee41829d30a05ded3e8.
ZCU102-ES is now supported in 2018.2 SDK. Hence restoring the folder to misc.

Signed-off-by: Vikram Sreenivasa Batchali <bvikram@xilinx.com>
Acked-by: Sarat Chand Savitala <saratcha@xilinx.com>
This patch updates the Reference clock lower limit value to
102.40625MHz.

Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com>
This patch updates changelog for rfdc driver.

Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com>
Acked-for-series: Srinivas Goud <sgoud@xilinx.com>
Signed-off-by: Siva Addepalli <saddepal@xilinx.com>
Acked-by: Venkatesh Dubakula <vdubakul@xilinx.com>
Signed-off-by: Siva Addepalli <saddepal@xilinx.com>
Acked-by: Venkatesh Dubakula <vdubakul@xilinx.com>
and xllfifo_polling_example.c in which false positives can occur
because the test transmit buffer is only filled with zeros.
This patch also fixes a bug in xllfifo_interrupt_example.c in the
receive data function in which it breaks the rule from pg080 which
states: RDFO should be read before reading RLR. Reading RLR first
will result in the RDFO being reset to zero. Without this fix, the
test fails when the transmit buffer is filled with non-zero data.
@radheyxilinx
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Hi @shearl , Thanks for sharing the fix. I will send the patches to xilinx internal mailing list and hopefully, it should get included in 2018.3 release.

@@ -272,7 +275,7 @@ int TxSend(XLlFifo *InstancePtr, u32 *SourceAddr)

/* Filling the buffer with data */
for (i=0;i<MAX_DATA_BUFFER_SIZE;i++)
*(SourceAddr + i) = 0;
*(SourceAddr + i) = i;
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Fix done (i.e RDFO read should be before RLR) in interrupt example is required in the poll example as well.

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