v_sdirx: Add API to wait for payload valid bits are set.

Add an API that should be used from application from the video
lock interrupt handler callback context. This API makes sure
that the st352 data from incoming rx stream is read and st352
registers are populated. Among all IP supported framerates 23.98
is the least vlaue which takes ~41 ms. With adding some buffer time,
this API waits for 50 ms and expects payload valid bits will be set
for sure which otherwise returns error.
SDI common library is also updated to support this.

Signed-off-by: Siva Rajesh <siva.rajesh.jarugula@xilinx.com>

Acked-for-series: Vishal Sagar <vsagar@xilinx.com>

XilinxProcessorIPLib/drivers/sdi_common/src/xv_sdivid.h

@@ -92,7 +92,8 @@ typedef enum {
 	XSDIVID_MODE_3GA = 2,
 	XSDIVID_MODE_3GB = 3,
 	XSDIVID_MODE_6G = 4,
-	XSDIVID_MODE_12G = 5
+	XSDIVID_MODE_12G = 5,
+	XSDIVID_MODE_12GF = 6
 } XSdiVid_TransMode;
 
 /**

XilinxProcessorIPLib/drivers/v_sdirx/src/xv_sdirx.c

@@ -710,6 +710,88 @@ u32 XV_SdiRx_GetPayloadId(XV_SdiRx *InstancePtr, u8 DataStream)
 	return RegValue;
 }
 
+/*****************************************************************************/
+/**
+* This function is used to wait for the payload valid bit to be set.
+* This has to be called from application based on the callback indication of
+* the video lock interrupt handler. Without this function being called, it may
+* be guaranteed that payload bits are valid after video lock interrupt occured.
+*
+* @param	InstancePtr is a pointer to the XV_SdiRx core instance.
+*
+* @return
+*		- XST_FAILURE if the payload valid bits are not set.
+*		- XST_SUCCESS if ST352 registers are read and loaded to
+*		  Rx structures
+*
+* @note         None.
+*
+******************************************************************************/
+u32 XV_SdiRx_WaitforPayLoad(XV_SdiRx *InstancePtr)
+{
+	u32 RegValue, Data0, Data1, Data3;
+	int StreamId;
+	XSdiVid_TransMode TMode;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	Data0 = XV_SdiRx_ReadReg(InstancePtr->Config.BaseAddress,
+			(XV_SDIRX_MODE_DET_STS_OFFSET));
+	Data1 = XV_SdiRx_ReadReg(InstancePtr->Config.BaseAddress,
+			(XV_SDIRX_TS_DET_STS_OFFSET));
+
+	/* Check if mode and transport are locked */
+	if (!(((Data0 & XV_SDIRX_MODE_DET_STS_MODE_LOCKED_MASK)
+		== XV_SDIRX_MODE_DET_STS_MODE_LOCKED_MASK)
+		&& ((Data1 & XV_SDIRX_TS_DET_STS_T_LOCKED_MASK)
+		== XV_SDIRX_TS_DET_STS_T_LOCKED_MASK)))
+		return XST_FAILURE;
+
+	TMode = Data0 & XV_SDIRX_MODE_DET_STS_MODE_MASK;
+
+	/* Based on TMode, calculate the expected values to be present in
+	 * the st352 valid register
+	 */
+	switch (TMode) {
+		case XSDIVID_MODE_HD:
+		case XSDIVID_MODE_SD:
+			Data3 = 0x1;
+			break;
+		case XSDIVID_MODE_3GA:
+			Data3 = 0x3;
+			break;
+		case XSDIVID_MODE_6G:
+		case XSDIVID_MODE_12G:
+		case XSDIVID_MODE_12GF:
+			Data3 = 0xF;
+			break;
+		default:
+			return XST_FAILURE;
+	}
+
+	/*
+	 * Wait for 50 ms, the maximum frame time for any SDI supported
+	 * resolution. The highest frametime is 1/23.98 ~ 41 ms. With some
+	 * buffer we consider 50 ms wait time affter which we can ensure that
+	 * a frame has been passed.
+	 */
+	usleep(50000);
+
+	/* Payload are expected for 3GA and above modes */
+	if ((XV_SdiRx_ReadReg(InstancePtr->Config.BaseAddress,
+				(XV_SDIRX_RX_ST352_VLD_OFFSET)) != Data3) &&
+		(TMode >= XSDIVID_MODE_3GA)) {
+		return XST_FAILURE;
+	}
+
+	for (StreamId = 0; StreamId < XV_SDIRX_MAX_DATASTREAM; StreamId++) {
+		InstancePtr->Stream[StreamId].PayloadId
+			= XV_SdiRx_GetPayloadId(InstancePtr, StreamId);
+	}
+
+	return XST_SUCCESS;
+}
+
 /*****************************************************************************/
 /**
 *
@@ -823,7 +905,7 @@ void XV_SdiRx_EnableMode(XV_SdiRx *InstancePtr,
 	Xil_AssertVoid(InstancePtr != NULL);
 	Xil_AssertVoid(SupportModes <= XV_SDIRX_SUPPORT_ALL);
 	/* Following assertions make sure the IP is configured with in the
-	 * subcore GUI paramter limit
+	 * subcore GUI parameter limit
 	 */
 	Xil_AssertVoid(!((InstancePtr->Config.MaxRateSupported == XSDIRX_LINE_RATE_3G) &&
 			(SupportModes & (XV_SDIRX_SUPPORT_6G |

XilinxProcessorIPLib/drivers/v_sdirx/src/xv_sdirx.h

@@ -269,6 +269,7 @@ int XV_SdiRx_CfgInitialize(XV_SdiRx *InstancePtr,
 	UINTPTR EffectiveAddr);
 void XV_SdiRx_ResetStream(XV_SdiRx *InstancePtr);
 u32 XV_SdiRx_GetPayloadId(XV_SdiRx *InstancePtr, u8 DataStream);
+u32 XV_SdiRx_WaitforPayLoad(XV_SdiRx *InstancePtr);
 u32 XV_SdiRx_GetSdiMode(XV_SdiRx *InstancePtr);
 void XV_SdiRx_FramerEnable(XV_SdiRx *InstancePtr);
 void XV_SdiRx_FramerDisable(XV_SdiRx *InstancePtr);