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PRIHZ_Boardfile #724

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219 changes: 219 additions & 0 deletions boards/iWave/ig65m-09eg02-4e004g-e032g-laa/1.0/board.xml
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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<!-- ********************************************************************** -->
<!-- iWave Systems Technologies -->
<!-- ********************************************************************** -->
<!-- SOM Supported : iW-PRIHZ-R1.0 -->
<!-- Date Created : 03Jan2025 -->
<!-- ********************************************************************** -->

<board schema_version="2.1" vendor="iwavesystems.com" name="iG65M-9EG02-4E004G-E032G-IAA" display_name="iG65M-9EG02-4E004G-E032G-IAA" url="https://www.iwavesystems.com/product/zu15-zu9-zu6-zynq-ultrascale-mpsoc-system-on-module" preset_file="preset.xml">

<images>
<image display_name="iW-G65-SOM" name="iW-G65-SOM.png" sub_type="board">
<description>iW-G65-SOM Image</description>
</image>
</images>

<compatible_board_revisions>
<revision id="0">2.0</revision>
</compatible_board_revisions>

<file_version>1.0</file_version>

<description>Zynq UltraScale+ MPSoC 9EG-1-I SOM, 4GB PS DDR4, 2 GB FPGA DDR4, 8GB eMMC Flash</description>

<parameters>
<parameter name="heat_sink_type" value_type="string" value="medium"/>
<parameter name="heat_sink_temperature" value_type="range" value_max="55.0" value_min="20.0"/>
</parameters>

<jumpers> </jumpers>

<components>
<component display_name="Zynq chip on board" name="part0" vendor="xilinx" type="fpga" spec_url="https://www.iwavesystems.com/product/zu15-zu9-zu6-zynq-ultrascale-mpsoc-system-on-module/" pin_map_file="part0_pins.xml" part_name="xczu9eg-ffvc900-2-i">
<description>FPGA part on the board</description>
<interfaces>
<interface name="ps8_fixedio" type="xilinx.com:zynq_ultra_ps_e:fixedio_rtl:1.0" preset_proc="zynq_ultra_ps_e_preset" of_component="ps8_fixedio" mode="master">
<preferred_ips>
<preferred_ip name="zynq_ultra_ps_e" vendor="xilinx.com" order="0" library="ip"/>
</preferred_ips>
</interface>

<interface mode="master" name="ddr4" type="xilinx.com:interface:ddr4_rtl:1.0" of_component="ddr4" preset_proc="ddr4_sdram_preset">
<description>DDR4 board interface, it can use DDR4 controller IP for connection. </description>
<preferred_ips>
<preferred_ip vendor="xilinx.com" library="ip" name="ddr4" order="0"/>
</preferred_ips>
<port_maps>
<port_map logical_port="ACT_N" physical_port="ddr4_act_n" dir="out">
<pin_maps>
<pin_map port_index="0" component_pin="ddr4_act_n"/>
</pin_maps>
</port_map>
<port_map logical_port="ADR" physical_port="ddr4_adr" dir="out" left="16" right="0">
<pin_maps>
<pin_map port_index="0" component_pin="ddr4_adr0"/>
<pin_map port_index="1" component_pin="ddr4_adr1"/>
<pin_map port_index="2" component_pin="ddr4_adr2"/>
<pin_map port_index="3" component_pin="ddr4_adr3"/>
<pin_map port_index="4" component_pin="ddr4_adr4"/>
<pin_map port_index="5" component_pin="ddr4_adr5"/>
<pin_map port_index="6" component_pin="ddr4_adr6"/>
<pin_map port_index="7" component_pin="ddr4_adr7"/>
<pin_map port_index="8" component_pin="ddr4_adr8"/>
<pin_map port_index="9" component_pin="ddr4_adr9"/>
<pin_map port_index="10" component_pin="ddr4_adr10"/>
<pin_map port_index="11" component_pin="ddr4_adr11"/>
<pin_map port_index="12" component_pin="ddr4_adr12"/>
<pin_map port_index="13" component_pin="ddr4_adr13"/>
<pin_map port_index="14" component_pin="ddr4_adr14"/>
<pin_map port_index="15" component_pin="ddr4_adr15"/>
<pin_map port_index="16" component_pin="ddr4_adr16"/>
</pin_maps>
</port_map>
<port_map logical_port="BA" physical_port="ddr4_ba" dir="out" left="1" right="0">
<pin_maps>
<pin_map port_index="0" component_pin="ddr4_ba0"/>
<pin_map port_index="1" component_pin="ddr4_ba1"/>
</pin_maps>
</port_map>
<port_map logical_port="BG" physical_port="ddr4_bg" dir="out">
<pin_maps>
<pin_map port_index="0" component_pin="ddr4_bg"/>
</pin_maps>
</port_map>
<port_map logical_port="CK_C" physical_port="ddr4_ck_c" dir="out">
<pin_maps>
<pin_map port_index="0" component_pin="ddr4_ck_c"/>
</pin_maps>
</port_map>
<port_map logical_port="CK_T" physical_port="ddr4_ck_t" dir="out">
<pin_maps>
<pin_map port_index="0" component_pin="ddr4_ck_t"/>
</pin_maps>
</port_map>
<port_map logical_port="CKE" physical_port="ddr4_cke" dir="out">
<pin_maps>
<pin_map port_index="0" component_pin="ddr4_cke"/>
</pin_maps>
</port_map>
<port_map logical_port="CS_N" physical_port="ddr4_cs_n" dir="out">
<pin_maps>
<pin_map port_index="0" component_pin="ddr4_cs_n"/>
</pin_maps>
</port_map>
<port_map logical_port="DM_N" physical_port="ddr4_dm_n" dir="inout" left="1" right="0">
<pin_maps>
<pin_map port_index="0" component_pin="ddr4_dm_n0"/>
<pin_map port_index="1" component_pin="ddr4_dm_n1"/>
</pin_maps>
</port_map>
<port_map logical_port="DQ" physical_port="ddr4_dq" dir="inout" left="15" right="0">
<pin_maps>
<pin_map port_index="0" component_pin="ddr4_dq0"/>
<pin_map port_index="1" component_pin="ddr4_dq1"/>
<pin_map port_index="2" component_pin="ddr4_dq2"/>
<pin_map port_index="3" component_pin="ddr4_dq3"/>
<pin_map port_index="4" component_pin="ddr4_dq4"/>
<pin_map port_index="5" component_pin="ddr4_dq5"/>
<pin_map port_index="6" component_pin="ddr4_dq6"/>
<pin_map port_index="7" component_pin="ddr4_dq7"/>
<pin_map port_index="8" component_pin="ddr4_dq8"/>
<pin_map port_index="9" component_pin="ddr4_dq9"/>
<pin_map port_index="10" component_pin="ddr4_dq10"/>
<pin_map port_index="11" component_pin="ddr4_dq11"/>
<pin_map port_index="12" component_pin="ddr4_dq12"/>
<pin_map port_index="13" component_pin="ddr4_dq13"/>
<pin_map port_index="14" component_pin="ddr4_dq14"/>
<pin_map port_index="15" component_pin="ddr4_dq15"/>
</pin_maps>
</port_map>
<port_map logical_port="DQS_C" physical_port="ddr4_dqs_c" dir="inout" left="1" right="0">
<pin_maps>
<pin_map port_index="0" component_pin="ddr4_dqs_c0"/>
<pin_map port_index="1" component_pin="ddr4_dqs_c1"/>
</pin_maps>
</port_map>
<port_map logical_port="DQS_T" physical_port="ddr4_dqs_t" dir="out" left="1" right="0">
<pin_maps>
<pin_map port_index="0" component_pin="ddr4_dqs_t0"/>
<pin_map port_index="1" component_pin="ddr4_dqs_t1"/>
</pin_maps>
</port_map>
<port_map logical_port="ODT" physical_port="ddr4_odt" dir="out">
<pin_maps>
<pin_map port_index="0" component_pin="ddr4_odt"/>
</pin_maps>
</port_map>
<port_map logical_port="RESET_N" physical_port="ddr4_reset_n" dir="out">
<pin_maps>
<pin_map port_index="0" component_pin="ddr4_reset_n"/>
</pin_maps>
</port_map>
</port_maps>
</interface>

<interface mode="slave" name="ddr4_sysclk" type="xilinx.com:interface:diff_clock_rtl:1.0" of_component="ddr4_sysclk">
<parameters>
<parameter name="frequency" value="300000000"/>
</parameters>
<preferred_ips>
<preferred_ip name="clk_wiz" vendor="xilinx.com" order="0" library="ip"/>
</preferred_ips>
<port_maps>
<port_map logical_port="CLK_P" physical_port="ddr4_sysclk_p" dir="in">
<pin_maps>
<pin_map port_index="0" component_pin="ddr4_sysclk_clk_p"/>
</pin_maps>
</port_map>
<port_map logical_port="CLK_N" physical_port="ddr4_sysclk_n" dir="in">
<pin_maps>
<pin_map port_index="0" component_pin="ddr4_sysclk_clk_n"/>
</pin_maps>
</port_map>
</port_maps>
</interface>

</interfaces>
</component>

<component display_name="PS8 fixed IO" name="ps8_fixedio" sub_type="fixed_io" type="chip" major_group=""/>

<component name="ddr4" display_name="DDR4 SDRAM" type="chip" sub_type="ddr" major_group="External Memory" part_name="MT40A1G16RC-062E" vendor="Micron" spec_url="https://in.element14.com/micron/mt40a1g16rc-062e-it-b/dram-ddr3-16gbit-40-to-95deg-c/dp/3577562?srsltid=AfmBOooGlxSy9ScZZ5su90_lUgnim00adElzN7m7GlQk8cLrOUElk5GX">
<description>2GB FPGA DDR4</description>
<parameters>
<parameter name="ddr_type" value="ddr4"/>
<parameter name="size" value="2GB"/>
</parameters>
</component>

<component name="ddr4_sysclk" display_name="DDR4 Reference Clock" type="chip" sub_type="system_clock" major_group="Clock Sources" part_name="XUL510300.000000I" vendor="Renesas" spec_url="https://www.renesas.com/us/en/document/dst/xu-family-low-phase-noise-quartz-based-pll-oscillators-datasheet">
<description>FPGA DDR4 Reference Clock</description>
<parameters>
<parameter name="frequency" value="300000000"/>
</parameters>
</component>

</components>

<jtag_chains>
<jtag_chain name="chain1">
<position name="0" component="part0"/>
</jtag_chain>
</jtag_chains>

<connections>

</connections>

<ip_associated_rules>
<ip_associated_rule name="default">
<ip vendor="xilinx.com" library="ip" name="ddr4" version="*" ip_interface="C0_SYS_CLK">
<associated_board_interfaces>
<associated_board_interface name="ddr4_sysclk" order="0"/>
</associated_board_interfaces>
</ip>
</ip_associated_rule>
</ip_associated_rules>

</board>
Binary file added boards/iWave/ig65m-09eg02-4e004g-e032g-laa/1.0/iW-G65-SOM.png
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79 changes: 79 additions & 0 deletions boards/iWave/ig65m-09eg02-4e004g-e032g-laa/1.0/part0_pins.xml
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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<!-- ********************************************************************** -->
<!-- iWave Systems Technologies -->
<!-- ********************************************************************** -->
<!-- SOM Supported : iW-PRIHZ-R1.0 -->
<!-- Date Created : 03Jan2025 -->
<!-- ********************************************************************** -->

<part_info part_name="xczu9eg-ffvc900-2-i">
<pins>
<!-- ********************************************************************** -->
<!-- DDR4 Pins -->
<!-- ********************************************************************** -->
<!-- Address Bus -->
<pin index="0" name ="ddr4_adr0" loc="U6"/>
<pin index="1" name ="ddr4_adr1" loc="U7"/>
<pin index="2" name ="ddr4_adr2" loc="U4"/>
<pin index="3" name ="ddr4_adr3" loc="U5"/>
<pin index="4" name ="ddr4_adr4" loc="W4"/>
<pin index="5" name ="ddr4_adr5" loc="V4"/>
<pin index="6" name ="ddr4_adr6" loc="Y5"/>
<pin index="7" name ="ddr4_adr7" loc="W5"/>
<pin index="8" name ="ddr4_adr8" loc="U1"/>
<pin index="9" name ="ddr4_adr9" loc="T1"/>
<pin index="10" name ="ddr4_adr10" loc="U3"/>
<pin index="11" name ="ddr4_adr11" loc="U2"/>
<pin index="12" name ="ddr4_adr12" loc="V1"/>
<pin index="13" name ="ddr4_adr13" loc="V2"/>
<pin index="14" name ="ddr4_adr14" loc="W1"/>
<pin index="15" name ="ddr4_adr15" loc="W2"/>
<pin index="16" name ="ddr4_adr16" loc="Y1"/>
<!-- Bank Address -->
<pin index="17" name ="ddr4_ba0" loc="T10"/>
<pin index="18" name ="ddr4_ba1" loc="V8"/>
<!-- Bank Group -->
<pin index="19" name ="ddr4_bg" loc="Y2"/>
<!-- Differential Clock Input -->
<pin index="20" name ="ddr4_ck_c" loc="V6"/>
<pin index="21" name ="ddr4_ck_t" loc="V7"/>
<!-- Clock Enable -->
<pin index="22" name ="ddr4_cke" loc="N11"/>
<!-- Chip Select -->
<pin index="23" name ="ddr4_cs_n" loc="Y3"/>
<!-- Data Mask -->
<pin index="24" name ="ddr4_dm_n0" loc="R10"/>
<pin index="25" name ="ddr4_dm_n1" loc="U8"/>
<!-- Data Bus -->
<pin index="26" name ="ddr4_dq0" loc="K10"/>
<pin index="27" name ="ddr4_dq1" loc="L10"/>
<pin index="28" name ="ddr4_dq2" loc="L11"/>
<pin index="29" name ="ddr4_dq3" loc="L12"/>
<pin index="30" name ="ddr4_dq4" loc="M12"/>
<pin index="31" name ="ddr4_dq5" loc="N12"/>
<pin index="32" name ="ddr4_dq6" loc="P10"/>
<pin index="33" name ="ddr4_dq7" loc="P11"/>
<pin index="34" name ="ddr4_dq8" loc="U10"/>
<pin index="35" name ="ddr4_dq9" loc="T11"/>
<pin index="36" name ="ddr4_dq10" loc="V9"/>
<pin index="37" name ="ddr4_dq11" loc="U9"/>
<pin index="38" name ="ddr4_dq12" loc="V11"/>
<pin index="39" name ="ddr4_dq13" loc="U11"/>
<pin index="40" name ="ddr4_dq14" loc="Y8"/>
<pin index="41" name ="ddr4_dq15" loc="Y9"/>
<!-- Differential Data Strode -->
<pin index="42" name ="ddr4_dqs_t0" loc="N10"/>
<pin index="43" name ="ddr4_dqs_t1" loc="W11"/>
<pin index="44" name ="ddr4_dqs_c0" loc="M10"/>
<pin index="45" name ="ddr4_dqs_c1" loc="W10"/>
<!-- On Die Termination -->
<pin index="46" name ="ddr4_odt" loc="Y7"/>
<!-- Activate Command Input -->
<pin index="47" name ="ddr4_act_n" loc="Y10"/>
<!-- Reset -->
<pin index="48" name ="ddr4_reset_n" loc="AE8" iostandard="LVCMOS18"/>
<!-- Reference Clock -->
<pin index="49" name ="ddr4_sysclk_clk_p" loc="W7"/>
<pin index="50" name ="ddr4_sysclk_clk_n" loc="W6"/>
</pins>
</part_info>
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