Fix AIE Makefile POSIX shell compatibility in Versal VSS tutorial

AI_Engine_Development/AIE-ML/AIE-ML.rst

@@ -16,15 +16,15 @@ The tutorials under the AI Engine for Machine Learning (AIE-ML) Development help
 
 .. important:: 
 
-   Before beginning a tutorial, ensure you have installed the Vitis 2024.2 software. The Vitis release includes all the embedded base platforms, including the VEK280 base platform that is used in these tutorials. In addition, ensure you have downloaded the Common Images for Embedded Vitis Platforms from `Downloads <https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/embedded-platforms.html>`_.
+   Before beginning a tutorial, ensure you have installed the Vitis 2025.2 software. The Vitis release includes all the embedded base platforms, including the VEK280 base platform that is used in these tutorials. In addition, ensure you have downloaded the Common Images for Embedded Vitis Platforms from `Downloads <https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/embedded-platforms.html>`_.
 
 The `common image` package contains a prebuilt Linux kernel and root file system that can be used with the AMD Versal™ board for embedded design development using the Vitis software platform.
 
 Before starting a tutorial, run the following steps:
 
 1. Go to the directory where you have unzipped the Versal Common Image package.
-2. In a Bash shell, run the ``/Common Images Dir/xilinx-versal-common-v2024.2/environment-setup-cortexa72-cortexa53-amd-linux`` script. This script sets up the SDKTARGETSYSROOT and CXX variables. If the script is not present, you must run ``/Common Images Dir/xilinx-versal-common-v2024.2/sdk.sh``.
-3. Set up your ROOTFS and IMAGE to point to the ``rootfs.ext4`` and Image files located in the ``/Common Images Dir/xilinx-versal-common-v2024.2`` directory.
+2. In a Bash shell, run the ``/Common Images Dir/xilinx-versal-common-v2025.2/environment-setup-cortexa72-cortexa53-amd-linux`` script. This script sets up the SDKTARGETSYSROOT and CXX variables. If the script is not present, you must run ``/Common Images Dir/xilinx-versal-common-v2025.2/sdk.sh``.
+3. Set up your ROOTFS and IMAGE to point to the ``rootfs.ext4`` and Image files located in the ``/Common Images Dir/xilinx-versal-common-v2025.2`` directory.
 4. Set up your PLATFORM_REPO_PATHS environment variable to ``$XILINX_VITIS/base_platforms``.
 
 

AI_Engine_Development/AIE-ML/Design_Tutorials/01-AIE-ML-programming-and-optimization/AIEngineMLArchitecture.md

@@ -15,14 +15,11 @@
 
 # AI Engine-ML Architecture
 
-
-
-
 ## Introduction
 
-Versal™ AI Edge ACAPs have been develop to target any applications at the edge where balancing performance and power consumption, low latency, size and thermal constraints, and safety and reliability are paramount.
+The Versal™ AI Edge Series has been develop to target any applications at the edge where balancing performance and power consumption, low latency, size and thermal constraints, and safety and reliability are paramount.
 
-As the Versal™ AI Core series they contain also an array of SIMD VLIW DSP processors but with different functionality.
+Like the Versal™ AI Core Series, it also contains an array of SIMD VLIW DSP processors but with different functionality.
 
 ![AI Engine-ML overview](images/AIE-ML-Overview.png)
 

AI_Engine_Development/AIE-ML/Design_Tutorials/01-AIE-ML-programming-and-optimization/Makefile

@@ -22,7 +22,7 @@ OPT ?= 0
 # hw_emu|hw
 
 TARGET   ?= hw_emu
-PFM_NAME := xilinx_vek280_base_202510_1
+PFM_NAME := xilinx_vek280_base_202520_1
 PFM_NAME := $(strip $(PFM_NAME))
 PLATFORM := ${PLATFORM_REPO_PATHS}/${PFM_NAME}/${PFM_NAME}.xpfm
 PNAME := aieml_pl_${TARGET}
@@ -97,16 +97,16 @@ guard-PLATFORM_REPO_PATHS:
 	$(call check_defined, PLATFORM_REPO_PATHS, Set your where you downloaded your platform)
 
 guard-ROOTFS:
-	$(call check_defined, ROOTFS, Set to: xilinx-versal-common-v2025.1/rootfs.ext4)
+	$(call check_defined, ROOTFS, Set to: xilinx-versal-common-v2025.2/rootfs.ext4)
 
 guard-IMAGE:
-	$(call check_defined, IMAGE, Set to: xilinx-versal-common-v2025.1/Image)
+	$(call check_defined, IMAGE, Set to: xilinx-versal-common-v2025.2/Image)
 
 guard-CXX:
-	$(call check_defined, CXX, Run: xilinx-versal-common-v2025.1/environment-setup-cortexa72-cortexa53-amd-linux)
+	$(call check_defined, CXX, Run: xilinx-versal-common-v2025.2/environment-setup-cortexa72-cortexa53-amd-linux)
 
 guard-SDKTARGETSYSROOT:
-	$(call check_defined, SDKTARGETSYSROOT, Run: xilinx-versal-common-v2025.1/environment-setup-cortexa72-cortexa53-amd-linux)
+	$(call check_defined, SDKTARGETSYSROOT, Run: xilinx-versal-common-v2025.2/environment-setup-cortexa72-cortexa53-amd-linux)
 
 ###
 .PHONY: all_hw all_hw_emu run upd_host_hw aie postaie data aiesim aieviz aiesim-fifo compareaie x86 x86sim comparex86 allcases
@@ -194,11 +194,12 @@ package_${TARGET}: ${LIBADF} ${XCLBIN} ${HOST_EXE}
 
 
 clean:
-	rm -rf _x v++_* ${XOS} ${OS} ${LIBADF} *.o.* *.o *.xpe *.xo.*  \
+	rm -rf _x v++_* ${XOS} ${OS} ${LIBADF} *.o.* *.o *.xpe *.xo.*  analyzer_input\
 	       vek280*.xclbin* *.xsa *.log *.jou xnwOut Work Map_Report.csv \
 	       ilpProblem* sol.db drivers .Xil *bin *BIN *.bif launch_hw_emu.sh cfg emu_qemu_scripts \
-				 [!d]*.json  *.txt *.wdb *.wcfg *.pdi v++.package_summary sim qemu_dts_files sd_card sd_card.img \
-				 dtb_creation.sh .ipcache *summary *.sh .AIE_SIM_CMD_LINE_OPTIONS .crashReporter
+				 [!d]*.json  *.txt *.wdb *.wcfg *.pdi v++.package_summary sim qemu_dts_files \
+				 sd_card sd_card.img \
+				 dtb_creation.sh .ipcache *summary *.sh .AIE_SIM_CMD_LINE_OPTIONS .crashReporter baremetal_metadata_package.cpp
 	make -C ${AIE_DIR} clean
 	make -C ${KERNELS_DIR} clean
 	make -C ${HOST_DIR} clean

AI_Engine_Development/AIE-ML/Design_Tutorials/01-AIE-ML-programming-and-optimization/README.md

@@ -15,22 +15,22 @@
 
 # AI Engine-ML Programming
 
-***Version: Vitis 2025.1***
+***Version: Vitis 2025.2***
 
 ## Introduction
 
->**IMPORTANT**: Before beginning the tutorial make sure you have installed the AMD Vitis™ 2025.1 software. The Vitis release includes all the embedded base platforms including the VEK280 base platform that is used in this tutorial. In addition, ensure you have downloaded the Common Images for Embedded Vitis Platforms from [this link](https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/embedded-platforms.html).
+>**IMPORTANT**: Before beginning the tutorial make sure you have installed the AMD Vitis™ 2025.2 software. The Vitis release includes all the embedded base platforms including the VEK280 base platform that is used in this tutorial. In addition, ensure you have downloaded the Common Images for Embedded Vitis Platforms from [this link](https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/embedded-platforms.html).
 
 The ‘common image’ package contains a prebuilt Linux kernel and root file system that can be used with the AMD Versal™ board for embedded design development using the Vitis software platform.
 
 Before starting this tutorial, run the following steps:
 
 1. Go to the directory where you have unzipped the Versal Common Image package.
-2. In a Bash shell, run the ``/Common Images Dir/xilinx-versal-common-v2025.1/environment-setup-cortexa72-cortexa53-amd-linux`` script. This script sets up the SDKTARGETSYSROOT and CXX variables. If the script is not present, you must run the ``/Common Images Dir/xilinx-versal-common-v2025.1/sdk.sh``.
-3. Set up your ROOTFS and IMAGE to point to the ``rootfs.ext4`` and Image files located in the ``/Common Images Dir/xilinx-versal-common-v2025.1`` directory.
+2. In a Bash shell, run the ``/Common Images Dir/xilinx-versal-common-v2025.2/environment-setup-cortexa72-cortexa53-amd-linux`` script. This script sets up the SDKTARGETSYSROOT and CXX variables. If the script is not present, you must run the ``/Common Images Dir/xilinx-versal-common-v2025.2/sdk.sh``.
+3. Set up your ROOTFS and IMAGE to point to the ``rootfs.ext4`` and Image files located in the ``/Common Images Dir/xilinx-versal-common-v2025.2`` directory.
 4. Set up your PLATFORM_REPO_PATHS environment variable to ``$XILINX_VITIS/base_platforms``.
 
-This tutorial targets VEK280 board for 2025.1 version.
+This tutorial targets VEK280 board for 2025.2 version.
 
 Data generation for this tutorial requires [Python 3](https://www.python.org/downloads/). The following packages are required:
 
@@ -67,10 +67,9 @@ The various memory levels contains DMAs used to receive/transfer data to/from me
 
 Matrix multiplication is very common algorithm that can be found in numerous standard applications. The basic equation is:
 
-```
 $$ C = A.B $$
 $$ \left( c_{ij} \right)_{\substack{0\leq i \lt M \\ 0 \leq j \lt N}}  =  \sum_{k=0}^{k<K} a_{ik}.b_{kj}$$
-```
+
 
 ![Matrix Multiplication](images/MatrixMult.png)
 
@@ -109,9 +108,7 @@ The *AI Engine-ML* has specific hardware instructions for matrix multiplications
 
 In the example developed in this tutorial the 3 matrices A, B and C are all 64x64 with 8-bit data:
 
-```
 $$A_{64x64}.B_{64x64} = C_{64x64}$$
-```
 
 The mode `4x16x8` will be used so that we need to decompose matrix **A** into `4x16`sub-matrices, matrix **B** into `16x8`sub-matrices in oder to compute **C** using `4x8` sub-results:
 

AI_Engine_Development/AIE-ML/Design_Tutorials/01-AIE-ML-programming-and-optimization/aie/Makefile

@@ -31,6 +31,8 @@ OPT ?= 0
 SIZES := sizeM=$(sizeM) sizeK=$(sizeK) sizeN=$(sizeN) subM=$(subM) subK=$(subK) subN=$(subN) NIterations=$(NIterations) PLIOW=$(PLIOW) OPT=$(OPT)
 SIZES_D := -DsizeM=$(sizeM) -DsizeK=$(sizeK) -DsizeN=$(sizeN) -DsubM=$(subM) -DsubK=$(subK) -DsubN=$(subN) -DNIterations=$(NIterations) -DPLIOW=$(PLIOW) -DOPTIMIZED_SOURCE=$(OPT)
 
+SIZES_D_Preproc := $(foreach word,$(SIZES_D),--aie.Xpreproc $(word))
+
 WORKDIR := ./Work$(OPT)
 AIEOUTDIR := aiesimulator_output$(OPT)
 X86OUTDIR := x86simulator_output$(OPT)
@@ -40,7 +42,7 @@ GRAPH    = src/graph.cpp
 LIBADF  = libadf$(OPT).a
 AIE_CMPL_CMD := v++ --compile --mode aie --include "./src" --aie.workdir $(WORKDIR) ${GRAPH}
 AIE_FLAGS +=  --aie.log-level 5
-AIE_FLAGS += --aie.Xpreproc "$(SIZES_D)"
+AIE_FLAGS += $(SIZES_D_Preproc)
 AIE_FLAGS += --aie.Xchess "ClassicMatMult:backend.mist2.xargs=+Omodo"
 AIE_FLAGS += --aie.output-archive $(LIBADF)
 

AI_Engine_Development/AIE-ML/Design_Tutorials/01-AIE-ML-programming-and-optimization/sw/host.cpp

@@ -4,6 +4,7 @@ SPDX-License-Identifier: MIT
 */
 
 
+#include <iostream>
 #include <fstream>
 #include <cstring>
 

AI_Engine_Development/AIE-ML/Design_Tutorials/02-Prime-Factor-FFT/Makefile

@@ -7,9 +7,9 @@
 ECHO                               = @echo
 export TARGET                      ?= hw
 
-RELEASE=2025.1
+RELEASE=2025.2
 BOARD=vek280
-BASE_NUM=202510_1
+BASE_NUM=202520_1
 
 # Platform Selection...
 VERSAL_VITIS_PLATFORM      = xilinx_${BOARD}\_base_${BASE_NUM}

AI_Engine_Development/AIE-ML/Design_Tutorials/02-Prime-Factor-FFT/README.md

@@ -15,7 +15,7 @@
 
 # Prime Factor FFT-1008 on AIE-ML
 
-***Version: Vitis 2025.1***
+***Version: Vitis 2025.2***
 
 ## Table of Contents
 
@@ -32,15 +32,16 @@
 [License](#license)
 
 ## Introduction
+
 The Prime Factor Algorithm (PFA) [[1]] is a Fast Fourier Transform (FFT) algorithm [[2]] discovered by Good & Thomas before the more popular Cooley-Tukey algorithm with some interesting properties. The PFA is another "divide and conquer" approach for computing a Discrete Fourier Transform (DFT) of size $N = N_1 \cdot N_2$ as a two-dimensional DFT of size $N_1 \times N_2$ as long as $N_1$ and $N_2$ are relatively prime (ie. share no common divisors). The smaller transforms of size $N_1$ and $N_2$ may be computed by some other technique, for example using the Winograd FFT Algorithm, or the PFA technique may be applied recursively again to both $N_1$ and $N_2$. It turns out Versal AI Engines compute DFT with small dimensions $N < 32$ very efficiently using direct vector/matrix multiplication. Consequently, the PFA approach using DFT on the individual prime factors provides an efficient approach to the FFT on Versal AI Engines.
 
 A second advantage of the PFA approach is that unlike the popular Cooley-Tukey FFT, no extra multiplications by "twiddle factors" need be performed between stages. This fact falls out of the DFT factorization when $N_1$ and $N_2$ share no common factors. This provides a computational advantage compared to the more traditional Cooley-Tukey formulation, but the PFA incurs a drawback in that a complicated re-indexing or permutation of it's I/O samples is required. For Versal devices with both AI Engines and Programmable Logic (PL), however, this drawback is solved easily by leveraging the PL to implement these permutations as part of a custom data flow tailored to the PFA signal flow graph.
 
 An [earlier tutorial](../../../AIE/Design_Tutorials/05-Prime-Factor-FFT) implemented a PFA-1008 transform on AIE architecture in the VC1902 device. This tutorial maps the PFA-1008 transform to AIE-ML architecture in the VE2802 device. Once again we map the short-length DFT-7, DFT-9 and DFT-16 transforms to AI Engine using vector-matrix DFT's but this time to the AIE-ML architecture. The intermediate "memory transpose" operations mapped earlier to the programmable logic (PL) are instead mapped here to the Memory Tiles contained in the AIE-ML array. This simplifies data flow and keeps most of the graph inside the the array. The input and output permutation blocks remain implemented in the PL as RTL obtained using VItis High Level Synthesis (HLS) from untimed C++ models. These cannot be mapped to Mem Tiles as they require a type of modulo addressing not supported by the Memory Tile buffer descriptors (BDs).
 
-## Matlab Models
+## MATLAB Models
 
-This tutorial relies on the same Matlab models from the [original tutorial](../../../AIE/Design_Tutorials/05-Prime-Factor-FFT). These models have been replicated here in the `matlab` folder of the repo. These apply to both the signal processing functions as well as the I/O permutations and matrix transpose addressing operations. All remain identical.
+This tutorial relies on the same MATLAB® models from the [original tutorial](../../../AIE/Design_Tutorials/05-Prime-Factor-FFT). These models have been replicated here in the `matlab` folder of the repo. These apply to both the signal processing functions as well as the I/O permutations and matrix transpose addressing operations. All remain identical.
 
 ## Design Overview
 
@@ -157,16 +158,16 @@ The figure below summarizes the PL resources required to implement the design. T
 
 ### Setup & Initialization
 
-IMPORTANT: Before beginning the tutorial ensure you have installed Vitis™ 2025.1 software. Ensure you have downloaded the Common Images for Embedded Vitis Platforms from [this link](https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/embedded-platforms.html).
+IMPORTANT: Before beginning the tutorial ensure you have installed Vitis™ 2025.2 software. Ensure you have downloaded the Common Images for Embedded Vitis Platforms from [this link](https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/embedded-platforms.html).
 
 Set the environment variable ```COMMON_IMAGE_VERSAL``` to the full path where you have downloaded the Common Images. Then set the environment variable ```PLATFORM_REPO_PATHS``` to the value ```$XILINX_VITIS/base_platforms```. Additional information on this process may be found [here](../../../AIE#environment-settings).
 
 The remaining environment variables are configured in the top level Makefile ```<path-to-design>/02-Prime-Factor-FFT/Makefile``` file.
 
 ```
-RELEASE=2025.1
+RELEASE=2025.2
 BOARD=vek280
-BASE_NUM=202510_1
+BASE_NUM=202520_1
 
 # Platform Selection...
 VERSAL_VITIS_PLATFORM      = xilinx_${BOARD}\_base_${BASE_NUM}

AI_Engine_Development/AIE-ML/Design_Tutorials/02-Prime-Factor-FFT/aie/dft16/Makefile

@@ -10,8 +10,7 @@ MY_APP            := dft16_app
 MY_SOURCES        := ${MY_APP}.cpp dft16_graph.h dft16_mmul0.h dft16_mmul0.cpp dft16_mmul1.h dft16_mmul1.cpp \
                      dft16_twiddle.h
 
-PLATFORM_USE	  := xilinx_vek280_base_202510_1
-PLATFORM          := ${PLATFORM_REPO_PATHS}/${PLATFORM_USE}/${PLATFORM_USE}.xpfm
+PART_USE          := xcve2802-vsvh1760-2MP-e-S
 
 CHECK_FIFO        := --aie.evaluate-fifo-depth --aie.Xrouter=disablePathBalancing
 
@@ -21,8 +20,7 @@ DSPLIB_OPTS 	  := --include=${DSPLIB_ROOT}/L2/include/aie \
 
 AIE_OUTPUT := libadf.a
 
-AIE_FLAGS :=	${DSPLIB_OPTS} --platform=${PLATFORM} ${MY_APP}.cpp --aie.output-archive=${AIE_OUTPUT}
-
+AIE_FLAGS :=	${DSPLIB_OPTS} --part=${PART_USE} ${MY_APP}.cpp --aie.output-archive=${AIE_OUTPUT}
 ifeq (${SIM_FIFO}, true)
 	AIE_FLAGS := ${AIE_FLAGS} ${CHECK_FIFO}
 endif

AI_Engine_Development/AIE-ML/Design_Tutorials/02-Prime-Factor-FFT/aie/dft7/Makefile

@@ -10,8 +10,7 @@ MY_APP            := dft7_app
 MY_SOURCES        := ${MY_APP}.cpp dft7_graph.h dft7_mmul0.h dft7_mmul0.cpp dft7_mmul1.h dft7_mmul1.cpp \
 	             dft7_twiddle.h
 
-PLATFORM_USE	  := xilinx_vek280_base_202510_1
-PLATFORM          := ${PLATFORM_REPO_PATHS}/${PLATFORM_USE}/${PLATFORM_USE}.xpfm
+PART_USE          := xcve2802-vsvh1760-2MP-e-S
 
 CHECK_FIFO        := --aie.evaluate-fifo-depth --aie.Xrouter=disablePathBalancing
 
@@ -21,8 +20,7 @@ DSPLIB_OPTS 	  := --include=${DSPLIB_ROOT}/L2/include/aie \
 
 AIE_OUTPUT := libadf.a
 
-AIE_FLAGS :=	${DSPLIB_OPTS} --platform=${PLATFORM} ${MY_APP}.cpp --aie.output-archive=${AIE_OUTPUT}
-
+AIE_FLAGS :=	${DSPLIB_OPTS} --part=${PART_USE} ${MY_APP}.cpp --aie.output-archive=${AIE_OUTPUT}
 ifeq (${SIM_FIFO}, true)
 	AIE_FLAGS := ${AIE_FLAGS} ${CHECK_FIFO}
 endif

AI_Engine_Development/AIE-ML/Design_Tutorials/02-Prime-Factor-FFT/aie/dft9/Makefile

@@ -10,15 +10,13 @@ MY_APP            := dft9_app
 MY_SOURCES        := ${MY_APP}.cpp dft9_graph.h dft9_mmul0.h dft9_mmul1.h dft9_mmul0.cpp dft9_mmul1.cpp \
 	             dft9_mmul3.h dft9_mmul3.cpp dft9_twiddle.h
 
-PLATFORM_USE	  := xilinx_vek280_base_202510_1
-PLATFORM          := ${PLATFORM_REPO_PATHS}/${PLATFORM_USE}/${PLATFORM_USE}.xpfm
+PART_USE          := xcve2802-vsvh1760-2MP-e-S
 
 CHECK_FIFO        := --aie.evaluate-fifo-depth --aie.Xrouter=disablePathBalancing
 
 AIE_OUTPUT := libadf.a
 
-AIE_FLAGS :=	--platform=${PLATFORM} ${MY_APP}.cpp --aie.output-archive=${AIE_OUTPUT}
-
+AIE_FLAGS :=	${DSPLIB_OPTS} --part=${PART_USE} ${MY_APP}.cpp --aie.output-archive=${AIE_OUTPUT}
 ifeq (${SIM_FIFO}, true)
 	AIE_FLAGS := ${AIE_FLAGS} ${CHECK_FIFO}
 endif

AI_Engine_Development/AIE-ML/Design_Tutorials/02-Prime-Factor-FFT/aie/permute_i/Makefile

@@ -9,8 +9,7 @@ SIM_FIFO          := false
 MY_APP            := permute_i_app
 MY_SOURCES        := ${MY_APP}.cpp permute_i_graph.h permute_i_bd.h
 
-PLATFORM_USE	  := xilinx_vek280_base_202510_1
-PLATFORM          := ${PLATFORM_REPO_PATHS}/${PLATFORM_USE}/${PLATFORM_USE}.xpfm
+PART_USE          := xcve2802-vsvh1760-2MP-e-S
 
 CHECK_FIFO        := --aie.evaluate-fifo-depth --aie.Xrouter=disablePathBalancing
 
@@ -20,8 +19,7 @@ DSPLIB_OPTS 	  := --include=${DSPLIB_ROOT}/L2/include/aie \
 
 AIE_OUTPUT := libadf.a
 
-AIE_FLAGS :=	${DSPLIB_OPTS} --platform=${PLATFORM} ${MY_APP}.cpp --aie.output-archive=${AIE_OUTPUT}
-
+AIE_FLAGS :=	${DSPLIB_OPTS} --part=${PART_USE} ${MY_APP}.cpp --aie.output-archive=${AIE_OUTPUT}
 ifeq (${SIM_FIFO}, true)
 	AIE_FLAGS := ${AIE_FLAGS} ${CHECK_FIFO}
 endif

AI_Engine_Development/AIE-ML/Design_Tutorials/02-Prime-Factor-FFT/aie/pfa1008/Makefile

@@ -25,8 +25,7 @@ MY_SOURCES        := ${MY_APP}.cpp pfa1008_graph.h ${DFT7_SOURCE:%=../dft7/%} ${
 	             ${DFT16_SOURCE:%=../dft16/%} \
 	             ${TRANSPOSE0_SOURCE:%=../transpose0/%} ${TRANSPOSE1_SOURCE:%=../transpose1/%}
 
-PLATFORM_USE	  := xilinx_vek280_base_202510_1
-PLATFORM          := ${PLATFORM_REPO_PATHS}/${PLATFORM_USE}/${PLATFORM_USE}.xpfm
+PART_USE          := xcve2802-vsvh1760-2MP-e-S
 
 CHECK_FIFO        := --aie.evaluate-fifo-depth --aie.Xrouter=disablePathBalancing
 
@@ -38,7 +37,7 @@ MY_INCLUDES 	  := --include=../dft7 \
 
 AIE_OUTPUT := libadf.a
 
-AIE_FLAGS :=	${MY_INCLUDES} --platform=${PLATFORM} ${MY_APP}.cpp --aie.output-archive=${AIE_OUTPUT}
+AIE_FLAGS :=	${MY_INCLUDES} --part=${PART_USE} ${MY_APP}.cpp --aie.output-archive=${AIE_OUTPUT}
 
 ifeq (${SIM_FIFO}, true)
 	AIE_FLAGS := ${AIE_FLAGS} ${CHECK_FIFO}

AI_Engine_Development/AIE-ML/Design_Tutorials/02-Prime-Factor-FFT/aie/transpose0/Makefile

@@ -9,8 +9,7 @@ SIM_FIFO          := false
 MY_APP            := transpose0_app
 MY_SOURCES        := ${MY_APP}.cpp transpose0_graph.h
 
-PLATFORM_USE	  := xilinx_vek280_base_202510_1
-PLATFORM          := ${PLATFORM_REPO_PATHS}/${PLATFORM_USE}/${PLATFORM_USE}.xpfm
+PART_USE          := xcve2802-vsvh1760-2MP-e-S
 
 CHECK_FIFO        := --aie.evaluate-fifo-depth --aie.Xrouter=disablePathBalancing
 
@@ -20,8 +19,7 @@ DSPLIB_OPTS 	  := --include=${DSPLIB_ROOT}/L2/include/aie \
 
 AIE_OUTPUT := libadf.a
 
-AIE_FLAGS :=	${DSPLIB_OPTS} --platform=${PLATFORM} ${MY_APP}.cpp --aie.output-archive=${AIE_OUTPUT}
-
+AIE_FLAGS :=	${DSPLIB_OPTS} --part=${PART_USE} ${MY_APP}.cpp --aie.output-archive=${AIE_OUTPUT}
 ifeq (${SIM_FIFO}, true)
 	AIE_FLAGS := ${AIE_FLAGS} ${CHECK_FIFO}
 endif