Fixed done correctness bug

pyproject.toml

@@ -1,6 +1,6 @@
 [project]
 name = "python2verilog"
-version = "0.2.9"
+version = "0.2.10"
 authors = [{ name = "Kerry Wang", email = "kerrywang369@gmail.com" }]
 description = "Converts a subset of python generator functions into synthesizable sequential SystemVerilog"
 readme = "README.md"

python2verilog/backend/verilog/ast.py

@@ -524,7 +524,9 @@ def __init__(
 
     def to_lines(self):
         lines = Lines()
-        lines += f"if ({self.condition.verilog()}) begin"
+        lines += f"if ({self.condition.verilog()}) begin" + (
+            f" // {self.comment}" if self.comment else ""
+        )
         for stmt in self.then_body:
             lines.concat(stmt.to_lines(), indent=1)
         if self.else_body:

python2verilog/backend/verilog/codegen.py

@@ -101,7 +101,6 @@ def create_instance_zeroed_signals() -> Iterator[ver.Statement]:
                 ver.Statement("`ifdef DEBUG"),
                 ver.Statement(make_debug_display(context)),
                 ver.Statement("`endif"),
-                ver.NonBlockingSubsitution(context.signals.done, ir.UInt(0)),
                 ver.Statement(),
             ]
             + list(create_instance_zeroed_signals())
@@ -111,7 +110,14 @@ def create_instance_zeroed_signals() -> Iterator[ver.Statement]:
                     context.signals.ready,
                     cast(
                         list[ver.Statement],
-                        [ver.NonBlockingSubsitution(context.signals.valid, ir.UInt(0))],
+                        [
+                            ver.NonBlockingSubsitution(
+                                context.signals.valid, ir.UInt(0)
+                            ),
+                            ver.NonBlockingSubsitution(
+                                context.signals.done, ir.UInt(0)
+                            ),
+                        ],
                     ),
                     [],
                 ),
@@ -120,11 +126,19 @@ def create_instance_zeroed_signals() -> Iterator[ver.Statement]:
                 ver.Statement(),
                 ver.Statement(comment="Start signal takes precedence over reset"),
                 ver.IfElse(
-                    context.signals.reset,
+                    ir.UBinOp(context.signals.reset, "||", context.signals.start),
                     then_body=[
                         ver.NonBlockingSubsitution(
-                            lvalue=context.state_var,
-                            rvalue=context.idle_state,
+                            context.state_var,
+                            context.idle_state,
+                        ),
+                        ver.NonBlockingSubsitution(
+                            context.signals.done,
+                            ir.UInt(0),
+                        ),
+                        ver.NonBlockingSubsitution(
+                            context.signals.valid,
+                            ir.UInt(0),
                         ),
                     ],
                     else_body=[],
@@ -272,7 +286,7 @@ def __make_start_if_else(
             )
 
         if_else = ver.IfElse(
-            ir.Expression("_start"),
+            context.signals.start,
             then_body,
             [
                 ver.Statement(
@@ -289,7 +303,6 @@ def __make_start_if_else(
                 ),
             ],
         )
-        # logging.debug(f"make start if else {if_else}")
         return [if_else]
 
     @property
@@ -405,22 +418,17 @@ def make_display_stmt():
 
             # While loop waitng for ready signal
             while_body: list[ver.Statement] = []
-            # while_body.append(make_display_stmt())
-            if config.random_ready:
-                while_body.append(ver.Statement("_ready = $urandom_range(0, 4) === 0;"))
-            while_body.append(
-                ver.Statement(
-                    comment="`if (_ready && _valid)` also works as a conditional"
-                )
-            )
+            while_body.append(ver.AtPosedgeStatement(self.context.signals.clock))
             while_body.append(
                 ver.IfElse(
-                    condition=ir.Expression("_ready"),
+                    condition=self.context.signals.ready,
                     then_body=[make_display_stmt()],
                     else_body=[],
                 )
             )
             while_body.append(ver.AtNegedgeStatement(self.context.signals.clock))
+            if config.random_ready:
+                while_body.append(ver.Statement("_ready = $urandom_range(0, 4) === 0;"))
 
             initial_body.append(
                 ver.While(
@@ -432,13 +440,13 @@ def make_display_stmt():
                     body=while_body,
                 )
             )
-            initial_body.append(
-                ver.IfElse(
-                    condition=ir.Expression("_ready"),
-                    then_body=[make_display_stmt()],
-                    else_body=[],
-                )
-            )
+            # initial_body.append(
+            #     ver.IfElse(
+            #         condition=self.context.signals.ready,
+            #         then_body=[make_display_stmt()],
+            #         else_body=[],
+            #     )
+            # )
             initial_body.append(ver.Statement())
 
         initial_body.append(ver.Statement(literal="$finish;"))
@@ -510,17 +518,6 @@ def get_case(self) -> ver.Case:
         # Reverse states for readability (states are built backwards)
         self.case.case_items = list(reversed(self.case.case_items))
 
-        # Add done state if it doesn't exist in cases
-        if all(
-            case.condition != self.context.done_state for case in self.case.case_items
-        ):
-            self.case.case_items.append(
-                ver.CaseItem(
-                    condition=self.context.done_state,
-                    statements=[self.create_quick_done(self.context)],
-                )
-            )
-
         return self.case
 
     @staticmethod
@@ -536,7 +533,6 @@ def create_quick_done(context: ir.Context) -> ver.IfElse:
             condition=ir.UBinOp(
                 ir.UnaryOp("!", context.signals.valid), "&&", context.signals.ready
             ),
-            # condition=context.signals.ready,
             then_body=[
                 ver.NonBlockingSubsitution(context.signals.done, ir.UInt(1)),
                 ver.NonBlockingSubsitution(context.state_var, context.idle_state),
@@ -567,10 +563,7 @@ def do_vertex(self, vertex: ir.Node):
 
         stmts: list[ver.Statement] = []
 
-        if isinstance(vertex, ir.DoneNode):
-            stmts.append(self.create_quick_done(self.context))
-
-        elif isinstance(vertex, ir.AssignNode):
+        if isinstance(vertex, ir.AssignNode):
             stmts.append(
                 ver.NonBlockingSubsitution(
                     vertex.lvalue,
@@ -610,4 +603,6 @@ def do_edge(self, edge: ir.Edge):
                     self.context.state_var, ir.State(edge.optimal_child.unique_id)
                 )
             ]
+        if isinstance(edge, type(None)):
+            return []
         raise RuntimeError(f"{type(edge)}")

python2verilog/backend/verilog/config.py

@@ -24,4 +24,7 @@ class CodegenConfig(TestbenchConfig):
     """
 
     # Enable debug comments graph elements as comment
-    add_debug_comments: bool = env.get_var(env.Vars.DEBUG_COMMENTS)
+    add_debug_comments: bool = False
+
+    def __post_init__(self):
+        self.add_debug_comments |= bool(env.get_var(env.Vars.DEBUG_COMMENTS))