Skip to content

Commit

Permalink
Fix #1
Browse files Browse the repository at this point in the history
  • Loading branch information
Kei authored and Kei committed Aug 7, 2017
1 parent f2a1faa commit 7c9cfeb
Show file tree
Hide file tree
Showing 425 changed files with 63,992 additions and 674 deletions.
1 change: 1 addition & 0 deletions .gitignore
View file
Original file line number Diff line number Diff line change
@@ -0,0 +1 @@
/.project
674 changes: 0 additions & 674 deletions LICENSE
View file

This file was deleted.

1,113 changes: 1,113 additions & 0 deletions lib/CMSIS/Device/WIZnet/W7500/Include/W7500x.h
View file

Large diffs are not rendered by default.

106 changes: 106 additions & 0 deletions lib/CMSIS/Device/WIZnet/W7500/Include/system_W7500x.h
View file
Original file line number Diff line number Diff line change
@@ -0,0 +1,106 @@
/*******************************************************************************************************************************************************
* Copyright ¨Ï 2016 <WIZnet Co.,Ltd.>
* Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the ¡°Software¡±),
* to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
* THE SOFTWARE IS PROVIDED ¡°AS IS¡±, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*********************************************************************************************************************************************************/
/**************************************************************************/
/**
* @file system_W7500x.h
* @author IOP Team
* @version V1.0.0
* @date 01-May-2015
* @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File for
* Device W7500x
******************************************************************************
*
* @attention
* @par Revision history
* <2015/05/01> 1st Release
*
* <h2><center>&copy; COPYRIGHT 2015 WIZnet Co.,Ltd.</center></h2>
******************************************************************************
*/

#ifndef SYSTEM_W7500x_H /* ToDo: replace '<Device>' with your device name */
#define SYSTEM_W7500x_H

#ifdef __cplusplus
extern "C" {
#endif

#include "W7500x.h"

extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
extern uint32_t GetSystemClock(void); /*!< Get System Clock Frequency */
extern uint32_t GetSourceClock(void); /*!< Get PLL Source Clock Frequency */
extern uint32_t GetPLLSource(void); /*!< Get PLL Source Input; Internal or External */

/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable.
*/
extern void SystemInit (void);

/**
* Initialize the system for users custom
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System using parameters
*/
extern void SystemInit_User(uint8_t osc_in_sel, uint32_t pll_src_clock, uint32_t system_clock);


/**
* Re-Initialize the system clock for users custom
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Re-initialize the System using parameters
*/
extern void SystemCoreClockUpdate_User(uint8_t osc_in_sel, uint32_t pll_src_clock, uint32_t system_clock);



/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
#define EXTERN_XTAL 0x01// (8000000UL) /* External Oscillator Frequency */
#define INTERN_XTAL 0x00// (8000000UL) /* Internal Oscillator Frequency */

// Source clock frequency
#define PLL_SOURCE_8MHz (8000000UL) /* 8MHz Internal / External Oscillator Frequency */
#define PLL_SOURCE_12MHz (12000000UL) /* 12MHz External Oscillator Frequency */
#define PLL_SOURCE_24MHz (24000000UL) /* 24MHz External Oscillator Frequency */

// Targer system clock frequency
#define SYSTEM_CLOCK_8MHz (8000000UL)
#define SYSTEM_CLOCK_12MHz (12000000UL)
#define SYSTEM_CLOCK_16MHz (16000000UL)
#define SYSTEM_CLOCK_24MHz (24000000UL)
#define SYSTEM_CLOCK_32MHz (32000000UL)
#define SYSTEM_CLOCK_36MHz (36000000UL)
#define SYSTEM_CLOCK_48MHz (48000000UL) // W7500x maximum clock frequency

#ifdef __cplusplus
}
#endif

#endif /* SYSTEM_W7500x_H */
237 changes: 237 additions & 0 deletions lib/CMSIS/Device/WIZnet/W7500/Source/ARM/startup_W7500x.s
View file
Original file line number Diff line number Diff line change
@@ -0,0 +1,237 @@
;/******************************************************************************************************************************************************
;* Copyright ¨Ï 2016 <WIZnet Co.,Ltd.>
;* Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the ¡°Software¡±),
;* to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
;* and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions:
;*
;* The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
;
;* THE SOFTWARE IS PROVIDED ¡°AS IS¡±, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
;* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
;* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
;* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
;*********************************************************************************************************************************************************/
;/**************************************************************************/
;/**
; * @file startup_W7500x.s
; * @author IOP Team
; * @version V1.0.0
; * @date 01-May-2015
; * @brief CMSIS Cortex-M0 Core Device Startup File for Device W7500x
; ******************************************************************************
; *
; * @attention
; * @par Revision history
; * <2015/05/01> 1st Release
; *
; * <h2><center>&copy; COPYRIGHT 2015 WIZnet Co.,Ltd.</center></h2>
; ******************************************************************************
; */


; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>

Stack_Size EQU 0x00000400

AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp


; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>

Heap_Size EQU 0x00000400

AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit


PRESERVE8
THUMB


; Vector Table Mapped to Address 0 at Reset

AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size

__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
DCD SSP0_Handler ; 16+ 0: SSP 0 Handler
DCD SSP1_Handler ; 16+ 1: SSP 1 Handler
DCD UART0_Handler ; 16+ 2: UART 0 Handler
DCD UART1_Handler ; 16+ 3: UART 1 Handler
DCD UART2_Handler ; 16+ 4: UART 2 Handler
DCD I2C0_Handler ; 16+ 5: I2C 0 Handler
DCD I2C1_Handler ; 16+ 6: I2C 1 Handler
DCD PORT0_Handler ; 16+ 7: GPIO Port 0 Combined Handler
DCD PORT1_Handler ; 16+ 8: GPIO Port 1 Combined Handler
DCD PORT2_Handler ; 16+ 9: GPIO Port 2 Combined Handler
DCD PORT3_Handler ; 16+10: GPIO Port 3 Combined Handler
DCD DMA_Handler ; 16+11: DMA Combined Handler
DCD DUALTIMER0_Handler ; 16+12: Dual timer 0 handler
DCD DUALTIMER1_Handler ; 16+13: Dual timer 1 handler
DCD PWM0_Handler ; 16+14: PWM0 Handler
DCD PWM1_Handler ; 16+15: PWM1 Handler
DCD PWM2_Handler ; 16+16: PWM2 Handler
DCD PWM3_Handler ; 16+17: PWM3 Handler
DCD PWM4_Handler ; 16+18: PWM4 Handler
DCD PWM5_Handler ; 16+19: PWM5 Handler
DCD PWM6_Handler ; 16+20: PWM6 Handler
DCD PWM7_Handler ; 16+21: PWM7 Handler
DCD RTC_Handler ; 16+22: RTC Handler
DCD ADC_Handler ; 16+23: ADC Handler
DCD WZTOE_Handler ; 16+24: WZTOE_Handler
DCD EXTI_Handler ; 16+25: EXTI_Handler
__Vectors_End

__Vectors_Size EQU __Vectors_End - __Vectors

AREA |.text|, CODE, READONLY


; Reset Handler

Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP


; Dummy Exception Handlers (infinite loops which can be modified)

NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT SSP0_Handler [WEAK]
EXPORT SSP1_Handler [WEAK]
EXPORT UART0_Handler [WEAK]
EXPORT UART1_Handler [WEAK]
EXPORT UART2_Handler [WEAK]
EXPORT I2C0_Handler [WEAK]
EXPORT I2C1_Handler [WEAK]
EXPORT PORT0_Handler [WEAK]
EXPORT PORT1_Handler [WEAK]
EXPORT PORT2_Handler [WEAK]
EXPORT PORT3_Handler [WEAK]
EXPORT DMA_Handler [WEAK]
EXPORT DUALTIMER0_Handler [WEAK]
EXPORT DUALTIMER1_Handler [WEAK]
EXPORT PWM0_Handler [WEAK]
EXPORT PWM1_Handler [WEAK]
EXPORT PWM2_Handler [WEAK]
EXPORT PWM3_Handler [WEAK]
EXPORT PWM4_Handler [WEAK]
EXPORT PWM5_Handler [WEAK]
EXPORT PWM6_Handler [WEAK]
EXPORT PWM7_Handler [WEAK]
EXPORT RTC_Handler [WEAK]
EXPORT ADC_Handler [WEAK]
EXPORT WZTOE_Handler [WEAK]
EXPORT EXTI_Handler [WEAK]
SSP0_Handler
SSP1_Handler
UART0_Handler
UART1_Handler
UART2_Handler
I2C0_Handler
I2C1_Handler
PORT0_Handler
PORT1_Handler
PORT2_Handler
PORT3_Handler
DMA_Handler
DUALTIMER0_Handler
DUALTIMER1_Handler
PWM0_Handler
PWM1_Handler
PWM2_Handler
PWM3_Handler
PWM4_Handler
PWM5_Handler
PWM6_Handler
PWM7_Handler
RTC_Handler
ADC_Handler
WZTOE_Handler
EXTI_Handler
B .
ENDP


ALIGN


; User Initial Stack & Heap

IF :DEF:__MICROLIB

EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit

ELSE

IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap

__user_initial_stackheap PROC
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ENDP

ALIGN

ENDIF


END
Loading

0 comments on commit 7c9cfeb

Please sign in to comment.