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Implement support for rotate. #149
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+1 from me... I always wanted a VM with the same basic abilities as my own CPU. |
The corresponding design PR is now merged: WebAssembly/design#462. This PR lgtm, though it just needs a merge conflict resolution. |
Just updated ... should be good to go. Thanks! |
lgtm. thanks! |
@mbodart Could you try |
Sorry, I'm a relative newbie wrt git, and was just following a pattern in the Pro Git book. Following your instructions, the "git rebase master" needs the same conflict resolution as Please advise, thanks. |
@mbodart I'm no git expert, but the patch mbodart@863f4d4 does not look clean. Github seems to think it's ok to merge, so perhaps it is and @sunfishcode gave it lgtm just as I was posting. My understand is the conflicts need to be resolved, edit the file, then |
I resolved the conflicts when merging with my local bswaprotate branch. Thanks for being diligent, but I think we're all set. |
I still see a merge commit in the 3 commits here. It would be nicer to avoid that. You should be able to just do |
One more try, hope this works. |
If we also want to squash those two commits, |
LGTM, but please make sure to update the description, since this patch no longer contains byteswap. |
The new names are memory.atomic.notify, memory.atomic.wait32, and memory.atomic.wait64. See WebAssembly/threads#145.
Issue WebAssembly/reference-types#69 requires that `ref.null` instructions include a reference type immediate. This concept isn't present in the bulk-memory proposal, but the encoding is (in element segment expressions). This change updates the binary and text format, but not the syntax. This is OK for now, since the only reference type allowed here is `funcref`.
…bly#149 (WebAssembly#151) Previously it was not clear what to do when passing an `i32` to, e.g., an `i8x16.splat`: the `i32` has more bits than fit in an `i8` lane. As discussed in WebAssembly#149, this change removes the extra bits (potentially losing information) so that the input parameter will fit in the splatted lanes. If at some point the spec adds support for `i8` and `i16` types, then this change would be unnecessary since the splat signature could be, e.g., `i8x16.splat(x: i8)` and no truncation would be required.
Of the integer operations listed in FutureFeatures.md, it seems that bswap and the rotates fall into the camp of popcnt, clz and ctz, in that they are directly supported by current architectures.
This change implements i32 and i64 bswap, rol and ror, along with test cases.
I just noticed a minor name difference, where FutureFeatures.md uses rotl and rotr,
while I used rol and ror. I have no strong preference either way.
Of course, we need agreement as to whether this support is desired.
I'm about to raise this as an issue, and am submitting this PR in support.