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i64x2.min_u and i64x2.max_u instructions #418

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i64x2.min_u and i64x2.max_u instructions #418

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2 changes: 2 additions & 0 deletions proposals/simd/BinarySIMD.md
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Original file line number Diff line number Diff line change
Expand Up @@ -191,7 +191,9 @@ For example, `ImmLaneIdx16` is a byte with values in the range 0-15 (inclusive).
| `i64x2.add` | `0xce`| - |
| `i64x2.sub` | `0xd1`| - |
| `i64x2.mul` | `0xd5`| - |
| `i64x2.min_u` | `0xd7`| - |
| `f32x4.ceil` | `0xd8`| - |
| `i64x2.max_u` | `0xd9`| - |
| `f32x4.floor` | `0xd9`| - |
| `f32x4.trunc` | `0xda`| - |
| `f32x4.nearest` | `0xdb`| - |
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2 changes: 2 additions & 0 deletions proposals/simd/ImplementationStatus.md
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Expand Up @@ -160,6 +160,8 @@
| `i64x2.widen_high_i32x4_s` | | | | | |
| `i64x2.widen_low_i32x4_u` | | | | | |
| `i64x2.widen_high_i32x4_u` | | | | | |
| `i64x2.min_u` | | | | | |
| `i64x2.max_u` | | | | | |
| `f32x4.abs` | `-msimd128` | :heavy_check_mark: | | :heavy_check_mark: | :heavy_check_mark: |
| `f32x4.neg` | `-msimd128` | :heavy_check_mark: | | :heavy_check_mark: | :heavy_check_mark: |
| `f32x4.sqrt` | `-msimd128` | :heavy_check_mark: | | :heavy_check_mark: | :heavy_check_mark: |
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4 changes: 2 additions & 2 deletions proposals/simd/NewOpcodes.md
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Expand Up @@ -103,10 +103,10 @@
| ------------- | 0x74 | ------------- | 0x94 | ------------- | 0xb4 | ------------- | 0xd4 |
| ---- mul ---- | 0x75 | i16x8.mul | 0x95 | i32x4.mul | 0xb5 | i64x2.mul | 0xd5 |
| i8x16.min_s | 0x76 | i16x8.min_s | 0x96 | i32x4.min_s | 0xb6 | ------------- | 0xd6 |
| i8x16.min_u | 0x77 | i16x8.min_u | 0x97 | i32x4.min_u | 0xb7 | ------------- | 0xd7 |
| i8x16.min_u | 0x77 | i16x8.min_u | 0x97 | i32x4.min_u | 0xb7 | i64x2.min_u | 0xd7 |
| i8x16.max_s | 0x78 | i16x8.max_s | 0x98 | i32x4.max_s | 0xb8 | ------------- | 0xd8 |
| i8x16.max_u | 0x79 | i16x8.max_u | 0x99 | i32x4.max_u | 0xb9 | ------------- | 0xd9 |
| ---------------- | 0x7a | ---------------- | 0x9a | i32x4.dot_i16x8_s | 0xba | ------------- | 0xda |
| ---------------- | 0x7a | ---------------- | 0x9a | i32x4.dot_i16x8_s | 0xba | i64x2.max_u | 0xda |
| i8x16.avgr_u | 0x7b | i16x8.avgr_u | 0x9b | ---- avgr_u ---- | 0xbb | ------------- | 0xdb |

| f32x4 Op | opcode | f64x2 Op | opcode |
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2 changes: 2 additions & 0 deletions proposals/simd/SIMD.md
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Expand Up @@ -529,6 +529,7 @@ def S.q15mulr_sat_s(a, b):
* `i16x8.min_u(a: v128, b: v128) -> v128`
* `i32x4.min_s(a: v128, b: v128) -> v128`
* `i32x4.min_u(a: v128, b: v128) -> v128`
* `i64x2.min_u(a: v128, b: v128) -> v128`

Compares lane-wise signed/unsigned integers, and returns the minimum of
each pair.
Expand All @@ -545,6 +546,7 @@ def S.min(a, b):
* `i16x8.max_u(a: v128, b: v128) -> v128`
* `i32x4.max_s(a: v128, b: v128) -> v128`
* `i32x4.max_u(a: v128, b: v128) -> v128`
* `i64x2.max_u(a: v128, b: v128) -> v128`

Compares lane-wise signed/unsigned integers, and returns the maximum of
each pair.
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