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Merged
merged 5 commits into from
Apr 8, 2021
Merged

Add v128.load/storeN_lane SIMD instructions to C/JS API #3784

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1da5229
Add v128.load/storeN_lane SIMD instructions to C/JS API
dcodeIO Apr 8, 2021
57f48bf
Merge branch 'main' into simd-loadstorelane
dcodeIO Apr 8, 2021
0e5f8ab
rename instructions
dcodeIO Apr 8, 2021
828691f
test non-zero immediates
dcodeIO Apr 8, 2021
79dbe1f
clang-format-wrong
dcodeIO Apr 8, 2021
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16 changes: 8 additions & 8 deletions scripts/gen-s-parser.py
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Original file line number Diff line number Diff line change
Expand Up @@ -357,14 +357,14 @@
("v128.andnot", "makeBinary(s, BinaryOp::AndNotVec128)"),
("v128.any_true", "makeUnary(s, UnaryOp::AnyTrueVec128)"),
("v128.bitselect", "makeSIMDTernary(s, SIMDTernaryOp::Bitselect)"),
("v128.load8_lane", "makeSIMDLoadStoreLane(s, LoadLaneVec8x16)"),
("v128.load16_lane", "makeSIMDLoadStoreLane(s, LoadLaneVec16x8)"),
("v128.load32_lane", "makeSIMDLoadStoreLane(s, LoadLaneVec32x4)"),
("v128.load64_lane", "makeSIMDLoadStoreLane(s, LoadLaneVec64x2)"),
("v128.store8_lane", "makeSIMDLoadStoreLane(s, StoreLaneVec8x16)"),
("v128.store16_lane", "makeSIMDLoadStoreLane(s, StoreLaneVec16x8)"),
("v128.store32_lane", "makeSIMDLoadStoreLane(s, StoreLaneVec32x4)"),
("v128.store64_lane", "makeSIMDLoadStoreLane(s, StoreLaneVec64x2)"),
("v128.load8_lane", "makeSIMDLoadStoreLane(s, SIMDLoadStoreLaneOp::Load8LaneVec128)"),
("v128.load16_lane", "makeSIMDLoadStoreLane(s, SIMDLoadStoreLaneOp::Load16LaneVec128)"),
("v128.load32_lane", "makeSIMDLoadStoreLane(s, SIMDLoadStoreLaneOp::Load32LaneVec128)"),
("v128.load64_lane", "makeSIMDLoadStoreLane(s, SIMDLoadStoreLaneOp::Load64LaneVec128)"),
("v128.store8_lane", "makeSIMDLoadStoreLane(s, SIMDLoadStoreLaneOp::Store8LaneVec128)"),
("v128.store16_lane", "makeSIMDLoadStoreLane(s, SIMDLoadStoreLaneOp::Store16LaneVec128)"),
("v128.store32_lane", "makeSIMDLoadStoreLane(s, SIMDLoadStoreLaneOp::Store32LaneVec128)"),
("v128.store64_lane", "makeSIMDLoadStoreLane(s, SIMDLoadStoreLaneOp::Store64LaneVec128)"),
("i8x16.popcnt", "makeUnary(s, UnaryOp::PopcntVecI8x16)"),
("i8x16.abs", "makeUnary(s, UnaryOp::AbsVecI8x16)"),
("i8x16.neg", "makeUnary(s, UnaryOp::NegVecI8x16)"),
Expand Down
24 changes: 24 additions & 0 deletions src/binaryen-c.cpp
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Expand Up @@ -689,6 +689,14 @@ BinaryenOp BinaryenLoadExtUVec32x2ToVecI64x2(void) {
}
BinaryenOp BinaryenLoad32Zero(void) { return Load32Zero; }
BinaryenOp BinaryenLoad64Zero(void) { return Load64Zero; }
BinaryenOp BinaryenLoad8LaneVec128(void) { return Load8LaneVec128; }
BinaryenOp BinaryenLoad16LaneVec128(void) { return Load16LaneVec128; }
BinaryenOp BinaryenLoad32LaneVec128(void) { return Load32LaneVec128; }
BinaryenOp BinaryenLoad64LaneVec128(void) { return Load64LaneVec128; }
BinaryenOp BinaryenStore8LaneVec128(void) { return Store8LaneVec128; }
BinaryenOp BinaryenStore16LaneVec128(void) { return Store16LaneVec128; }
BinaryenOp BinaryenStore32LaneVec128(void) { return Store32LaneVec128; }
BinaryenOp BinaryenStore64LaneVec128(void) { return Store64LaneVec128; }
BinaryenOp BinaryenNarrowSVecI16x8ToVecI8x16(void) {
return NarrowSVecI16x8ToVecI8x16;
}
Expand Down Expand Up @@ -1176,6 +1184,22 @@ BinaryenExpressionRef BinaryenSIMDLoad(BinaryenModuleRef module,
.makeSIMDLoad(
SIMDLoadOp(op), Address(offset), Address(align), (Expression*)ptr));
}
BinaryenExpressionRef BinaryenSIMDLoadStoreLane(BinaryenModuleRef module,
BinaryenOp op,
uint32_t offset,
uint32_t align,
uint8_t index,
BinaryenExpressionRef ptr,
BinaryenExpressionRef vec) {
return static_cast<Expression*>(
Builder(*(Module*)module)
.makeSIMDLoadStoreLane(SIMDLoadStoreLaneOp(op),
Address(offset),
Address(align),
index,
(Expression*)ptr,
(Expression*)vec));
}
BinaryenExpressionRef BinaryenMemoryInit(BinaryenModuleRef module,
uint32_t segment,
BinaryenExpressionRef dest,
Expand Down
16 changes: 16 additions & 0 deletions src/binaryen-c.h
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Expand Up @@ -560,6 +560,14 @@ BINARYEN_API BinaryenOp BinaryenLoadExtSVec32x2ToVecI64x2(void);
BINARYEN_API BinaryenOp BinaryenLoadExtUVec32x2ToVecI64x2(void);
BINARYEN_API BinaryenOp BinaryenLoad32Zero(void);
BINARYEN_API BinaryenOp BinaryenLoad64Zero(void);
BINARYEN_API BinaryenOp BinaryenLoad8LaneVec128(void);
BINARYEN_API BinaryenOp BinaryenLoad16LaneVec128(void);
BINARYEN_API BinaryenOp BinaryenLoad32LaneVec128(void);
BINARYEN_API BinaryenOp BinaryenLoad64LaneVec128(void);
BINARYEN_API BinaryenOp BinaryenStore8LaneVec128(void);
BINARYEN_API BinaryenOp BinaryenStore16LaneVec128(void);
BINARYEN_API BinaryenOp BinaryenStore32LaneVec128(void);
BINARYEN_API BinaryenOp BinaryenStore64LaneVec128(void);
BINARYEN_API BinaryenOp BinaryenNarrowSVecI16x8ToVecI8x16(void);
BINARYEN_API BinaryenOp BinaryenNarrowUVecI16x8ToVecI8x16(void);
BINARYEN_API BinaryenOp BinaryenNarrowSVecI32x4ToVecI16x8(void);
Expand Down Expand Up @@ -803,6 +811,14 @@ BINARYEN_API BinaryenExpressionRef BinaryenSIMDLoad(BinaryenModuleRef module,
uint32_t align,
BinaryenExpressionRef ptr);
BINARYEN_API BinaryenExpressionRef
BinaryenSIMDLoadStoreLane(BinaryenModuleRef module,
BinaryenOp op,
uint32_t offset,
uint32_t align,
uint8_t index,
BinaryenExpressionRef ptr,
BinaryenExpressionRef vec);
BINARYEN_API BinaryenExpressionRef
BinaryenMemoryInit(BinaryenModuleRef module,
uint32_t segment,
BinaryenExpressionRef dest,
Expand Down
16 changes: 8 additions & 8 deletions src/gen-s-parser.inc
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Expand Up @@ -2998,7 +2998,7 @@ switch (op[0]) {
case '_': {
switch (op[12]) {
case 'l':
if (strcmp(op, "v128.load16_lane") == 0) { return makeSIMDLoadStoreLane(s, LoadLaneVec16x8); }
if (strcmp(op, "v128.load16_lane") == 0) { return makeSIMDLoadStoreLane(s, SIMDLoadStoreLaneOp::Load16LaneVec128); }
goto parse_error;
case 's':
if (strcmp(op, "v128.load16_splat") == 0) { return makeSIMDLoad(s, SIMDLoadOp::LoadSplatVec16x8); }
Expand All @@ -3025,7 +3025,7 @@ switch (op[0]) {
case '_': {
switch (op[12]) {
case 'l':
if (strcmp(op, "v128.load32_lane") == 0) { return makeSIMDLoadStoreLane(s, LoadLaneVec32x4); }
if (strcmp(op, "v128.load32_lane") == 0) { return makeSIMDLoadStoreLane(s, SIMDLoadStoreLaneOp::Load32LaneVec128); }
goto parse_error;
case 's':
if (strcmp(op, "v128.load32_splat") == 0) { return makeSIMDLoad(s, SIMDLoadOp::LoadSplatVec32x4); }
Expand Down Expand Up @@ -3053,7 +3053,7 @@ switch (op[0]) {
case '6': {
switch (op[12]) {
case 'l':
if (strcmp(op, "v128.load64_lane") == 0) { return makeSIMDLoadStoreLane(s, LoadLaneVec64x2); }
if (strcmp(op, "v128.load64_lane") == 0) { return makeSIMDLoadStoreLane(s, SIMDLoadStoreLaneOp::Load64LaneVec128); }
goto parse_error;
case 's':
if (strcmp(op, "v128.load64_splat") == 0) { return makeSIMDLoad(s, SIMDLoadOp::LoadSplatVec64x2); }
Expand All @@ -3069,7 +3069,7 @@ switch (op[0]) {
case '_': {
switch (op[11]) {
case 'l':
if (strcmp(op, "v128.load8_lane") == 0) { return makeSIMDLoadStoreLane(s, LoadLaneVec8x16); }
if (strcmp(op, "v128.load8_lane") == 0) { return makeSIMDLoadStoreLane(s, SIMDLoadStoreLaneOp::Load8LaneVec128); }
goto parse_error;
case 's':
if (strcmp(op, "v128.load8_splat") == 0) { return makeSIMDLoad(s, SIMDLoadOp::LoadSplatVec8x16); }
Expand Down Expand Up @@ -3106,16 +3106,16 @@ switch (op[0]) {
if (strcmp(op, "v128.store") == 0) { return makeStore(s, Type::v128, /*isAtomic=*/false); }
goto parse_error;
case '1':
if (strcmp(op, "v128.store16_lane") == 0) { return makeSIMDLoadStoreLane(s, StoreLaneVec16x8); }
if (strcmp(op, "v128.store16_lane") == 0) { return makeSIMDLoadStoreLane(s, SIMDLoadStoreLaneOp::Store16LaneVec128); }
goto parse_error;
case '3':
if (strcmp(op, "v128.store32_lane") == 0) { return makeSIMDLoadStoreLane(s, StoreLaneVec32x4); }
if (strcmp(op, "v128.store32_lane") == 0) { return makeSIMDLoadStoreLane(s, SIMDLoadStoreLaneOp::Store32LaneVec128); }
goto parse_error;
case '6':
if (strcmp(op, "v128.store64_lane") == 0) { return makeSIMDLoadStoreLane(s, StoreLaneVec64x2); }
if (strcmp(op, "v128.store64_lane") == 0) { return makeSIMDLoadStoreLane(s, SIMDLoadStoreLaneOp::Store64LaneVec128); }
goto parse_error;
case '8':
if (strcmp(op, "v128.store8_lane") == 0) { return makeSIMDLoadStoreLane(s, StoreLaneVec8x16); }
if (strcmp(op, "v128.store8_lane") == 0) { return makeSIMDLoadStoreLane(s, SIMDLoadStoreLaneOp::Store8LaneVec128); }
goto parse_error;
default: goto parse_error;
}
Expand Down
32 changes: 32 additions & 0 deletions src/js/binaryen.js-post.js
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Expand Up @@ -492,6 +492,14 @@ function initializeConstants() {
'LoadExtUVec32x2ToVecI64x2',
'Load32Zero',
'Load64Zero',
'Load8LaneVec128',
'Load16LaneVec128',
'Load32LaneVec128',
'Load64LaneVec128',
'Store8LaneVec128',
'Store16LaneVec128',
'Store32LaneVec128',
'Store64LaneVec128',
'NarrowSVecI16x8ToVecI8x16',
'NarrowUVecI16x8ToVecI8x16',
'NarrowSVecI32x4ToVecI16x8',
Expand Down Expand Up @@ -1498,6 +1506,30 @@ function wrapModule(module, self = {}) {
'load64_zero'(offset, align, ptr) {
return Module['_BinaryenSIMDLoad'](module, Module['Load64Zero'], offset, align, ptr);
},
'load8_lane'(offset, align, index, ptr, vec) {
return Module['_BinaryenSIMDLoadStoreLane'](module, Module['Load8LaneVec128'], offset, align, index, ptr, vec);
},
'load16_lane'(offset, align, index, ptr, vec) {
return Module['_BinaryenSIMDLoadStoreLane'](module, Module['Load16LaneVec128'], offset, align, index, ptr, vec);
},
'load32_lane'(offset, align, index, ptr, vec) {
return Module['_BinaryenSIMDLoadStoreLane'](module, Module['Load32LaneVec128'], offset, align, index, ptr, vec);
},
'load64_lane'(offset, align, index, ptr, vec) {
return Module['_BinaryenSIMDLoadStoreLane'](module, Module['Load64LaneVec128'], offset, align, index, ptr, vec);
},
'store8_lane'(offset, align, index, ptr, vec) {
return Module['_BinaryenSIMDLoadStoreLane'](module, Module['Store8LaneVec128'], offset, align, index, ptr, vec);
},
'store16_lane'(offset, align, index, ptr, vec) {
return Module['_BinaryenSIMDLoadStoreLane'](module, Module['Store16LaneVec128'], offset, align, index, ptr, vec);
},
'store32_lane'(offset, align, index, ptr, vec) {
return Module['_BinaryenSIMDLoadStoreLane'](module, Module['Store32LaneVec128'], offset, align, index, ptr, vec);
},
'store64_lane'(offset, align, index, ptr, vec) {
return Module['_BinaryenSIMDLoadStoreLane'](module, Module['Store64LaneVec128'], offset, align, index, ptr, vec);
},
'store'(offset, align, ptr, value) {
return Module['_BinaryenStore'](module, 16, offset, align, ptr, value, Module['v128']);
},
Expand Down
16 changes: 8 additions & 8 deletions src/passes/Print.cpp
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Expand Up @@ -747,28 +747,28 @@ struct PrintExpressionContents
void visitSIMDLoadStoreLane(SIMDLoadStoreLane* curr) {
prepareColor(o);
switch (curr->op) {
case LoadLaneVec8x16:
case Load8LaneVec128:
o << "v128.load8_lane";
break;
case LoadLaneVec16x8:
case Load16LaneVec128:
o << "v128.load16_lane";
break;
case LoadLaneVec32x4:
case Load32LaneVec128:
o << "v128.load32_lane";
break;
case LoadLaneVec64x2:
case Load64LaneVec128:
o << "v128.load64_lane";
break;
case StoreLaneVec8x16:
case Store8LaneVec128:
o << "v128.store8_lane";
break;
case StoreLaneVec16x8:
case Store16LaneVec128:
o << "v128.store16_lane";
break;
case StoreLaneVec32x4:
case Store32LaneVec128:
o << "v128.store32_lane";
break;
case StoreLaneVec64x2:
case Store64LaneVec128:
o << "v128.store64_lane";
break;
}
Expand Down
16 changes: 8 additions & 8 deletions src/wasm-interpreter.h
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Expand Up @@ -2821,8 +2821,8 @@ template<typename GlobalManager, typename SubType> class ModuleInstanceBase {
}
Literal vec = flow.getSingleValue();
switch (curr->op) {
case LoadLaneVec8x16:
case StoreLaneVec8x16: {
case Load8LaneVec128:
case Store8LaneVec128: {
std::array<Literal, 16> lanes = vec.getLanesUI8x16();
if (curr->isLoad()) {
lanes[curr->index] =
Expand All @@ -2834,8 +2834,8 @@ template<typename GlobalManager, typename SubType> class ModuleInstanceBase {
return {};
}
}
case LoadLaneVec16x8:
case StoreLaneVec16x8: {
case Load16LaneVec128:
case Store16LaneVec128: {
std::array<Literal, 8> lanes = vec.getLanesUI16x8();
if (curr->isLoad()) {
lanes[curr->index] =
Expand All @@ -2847,8 +2847,8 @@ template<typename GlobalManager, typename SubType> class ModuleInstanceBase {
return {};
}
}
case LoadLaneVec32x4:
case StoreLaneVec32x4: {
case Load32LaneVec128:
case Store32LaneVec128: {
std::array<Literal, 4> lanes = vec.getLanesI32x4();
if (curr->isLoad()) {
lanes[curr->index] =
Expand All @@ -2860,8 +2860,8 @@ template<typename GlobalManager, typename SubType> class ModuleInstanceBase {
return {};
}
}
case StoreLaneVec64x2:
case LoadLaneVec64x2: {
case Store64LaneVec128:
case Load64LaneVec128: {
std::array<Literal, 2> lanes = vec.getLanesI64x2();
if (curr->isLoad()) {
lanes[curr->index] =
Expand Down
16 changes: 8 additions & 8 deletions src/wasm.h
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Expand Up @@ -515,14 +515,14 @@ enum SIMDLoadOp {
};

enum SIMDLoadStoreLaneOp {
LoadLaneVec8x16,
LoadLaneVec16x8,
LoadLaneVec32x4,
LoadLaneVec64x2,
StoreLaneVec8x16,
StoreLaneVec16x8,
StoreLaneVec32x4,
StoreLaneVec64x2,
Load8LaneVec128,
Load16LaneVec128,
Load32LaneVec128,
Load64LaneVec128,
Store8LaneVec128,
Store16LaneVec128,
Store32LaneVec128,
Store64LaneVec128,
};

enum SIMDTernaryOp {
Expand Down
16 changes: 8 additions & 8 deletions src/wasm/wasm-binary.cpp
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Expand Up @@ -5897,35 +5897,35 @@ bool WasmBinaryBuilder::maybeVisitSIMDLoadStoreLane(Expression*& out,
size_t lanes;
switch (code) {
case BinaryConsts::V128Load8Lane:
op = LoadLaneVec8x16;
op = Load8LaneVec128;
lanes = 16;
break;
case BinaryConsts::V128Load16Lane:
op = LoadLaneVec16x8;
op = Load16LaneVec128;
lanes = 8;
break;
case BinaryConsts::V128Load32Lane:
op = LoadLaneVec32x4;
op = Load32LaneVec128;
lanes = 4;
break;
case BinaryConsts::V128Load64Lane:
op = LoadLaneVec64x2;
op = Load64LaneVec128;
lanes = 2;
break;
case BinaryConsts::V128Store8Lane:
op = StoreLaneVec8x16;
op = Store8LaneVec128;
lanes = 16;
break;
case BinaryConsts::V128Store16Lane:
op = StoreLaneVec16x8;
op = Store16LaneVec128;
lanes = 8;
break;
case BinaryConsts::V128Store32Lane:
op = StoreLaneVec32x4;
op = Store32LaneVec128;
lanes = 4;
break;
case BinaryConsts::V128Store64Lane:
op = StoreLaneVec64x2;
op = Store64LaneVec128;
lanes = 2;
break;
default:
Expand Down
16 changes: 8 additions & 8 deletions src/wasm/wasm-s-parser.cpp
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Expand Up @@ -2067,23 +2067,23 @@ SExpressionWasmBuilder::makeSIMDLoadStoreLane(Element& s,
Address defaultAlign;
size_t lanes;
switch (op) {
case LoadLaneVec8x16:
case StoreLaneVec8x16:
case Load8LaneVec128:
case Store8LaneVec128:
defaultAlign = 1;
lanes = 16;
break;
case LoadLaneVec16x8:
case StoreLaneVec16x8:
case Load16LaneVec128:
case Store16LaneVec128:
defaultAlign = 2;
lanes = 8;
break;
case LoadLaneVec32x4:
case StoreLaneVec32x4:
case Load32LaneVec128:
case Store32LaneVec128:
defaultAlign = 4;
lanes = 4;
break;
case LoadLaneVec64x2:
case StoreLaneVec64x2:
case Load64LaneVec128:
case Store64LaneVec128:
defaultAlign = 8;
lanes = 2;
break;
Expand Down
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