Banked-SRAM hierarchy model and OpenRAM configuration generator for HeteroCore. It consumes a compiler execution plan and quantifies activation, output, KV cache, instruction, weight, and DRAM-spill traffic.
It also includes a decode-specific KV sweep for Qwen2.5-1.5B-Instruct across context, batch, INT4/INT8/FP16 KV precision, and selective block-read fraction.
Timing, energy, and bandwidth results are analytical projections. Generated OpenRAM files are configurations, not completed or fabricated SRAM macros.
pip install -e .
heterocore-memory examples/sample.plan.json \
-o results/memory_report.json \
--openram-dir generated/openramVary capacity and banking:
heterocore-memory examples/sample.plan.json \
-o results/constrained.json \
--activation-kib 64 \
--output-kib 64 \
--kv-kib 256 \
--banks 2Run the checked decode matrix:
heterocore-decode-memory \
--contexts 512,2048,8192,32768 \
--batches 1,4,16 \
--precisions 4,8,16 \
--weight-bits 4 \
--selected-fractions 1,0.5,0.25 \
--output results/qwen_decode_memory.jsonThe decode report separates total KV capacity, weight and selected-KV reads, new-token writes, local residency, a modeled SRAM read-hit rate, external bytes per output token, a peak-bandwidth transfer-time projection, and configurable per-byte energy. All values are analytical; they do not claim measured cache or DRAM transactions.
The report includes per-operator SRAM bytes, DRAM bytes, transfer cycles, and energy estimates. Analog-mapped weights are treated as crossbar-resident; digital weights are charged as external transfers.
The full transformer plan in results/tiny_transformer_memory.json produces:
| Metric | Result |
|---|---|
| modeled SRAM traffic | 2,392,320 bytes |
| modeled DRAM traffic | 32,768 bytes |
| modeled DRAM fraction | 1.35% |
| projected memory energy | 15.89 uJ |
The digital attention-score operation accounts for the checked-in DRAM transfer. These numbers are analytical outputs under the default capacities, banking, latency, and energy assumptions.
The real ONNX transformer plan in
results/tiny_char_transformer_memory.json produces 148,928 modeled SRAM
bytes, 8,192 modeled DRAM bytes, a 5.21% DRAM fraction, and 1.73 uJ of
projected memory energy.
The checked Qwen decode sweep contains 108 context/batch/precision/selection cases. At context 8,192, batch 1, INT4 KV, INT4 weights, and 25% selected blocks, it projects 58.72 MB of KV capacity, 14.68 MB of selected KV reads, and 771.86 MB of weight reads per output token. With the configured 8 MiB local KV store and 896 GB/s peak external bandwidth, the total projected external traffic is 784.45 MB/token. These are logical scenario-model values, not hardware-counter measurements.
The generator emits reproducible Python configurations for Sky130, nominal process conditions, and power-of-two depths:
python "$OPENRAM_HOME/openram.py" generated/openram/activation_buffer.pyOpenRAM and a compatible PDK must be installed separately. See ARCHITECTURE.md for the modeled hierarchy and limitations.
python -m unittest discover -s tests
heterocore-memory examples/sample.plan.json \
-o results/memory_report.json \
--openram-dir generated/openramThis project can compare capacity, banking, and traffic assumptions. It does not establish post-layout timing, physical SRAM power, PDK correctness, fabrication yield, or measured bandwidth.