<Timer> Driver fix to start from 0

Issue: #159
VisorFolks · Aug 19, 2022 · f844671 · f844671
1 parent e6d87b4
commit f844671
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Showing 4 changed files with 3 additions and 1 deletion.
diff --git a/projects/demo_avr/config.mk b/projects/demo_avr/config.mk
@@ -16,5 +16,4 @@ STDLOG_MEMBUF	:= 0
 BOOTMSGS	:= 0
 EARLYCON_SERIAL	:= 1
 CONSOLE_SERIAL	:= 1
-TERRAKERN	:= 0
 OBRDLED_ENABLE	:= 1
diff --git a/src/platform/mega_avr/common/hal/timer/timer16.h b/src/platform/mega_avr/common/hal/timer/timer16.h
@@ -72,6 +72,7 @@ static void timer16_config_op_mode(const timer_port_t *port, bool en, bool inv)
 		reg &= ~(3 << ((3 - id) << 1));
 
 	MMIO8(port->baddr + TCCRA_16B_OFFSET) = reg;
+	MMIO16(port->baddr + TCNTL_16B_OFFSET) = 0;
 }
 
 static void timer16_set(const timer_port_t *port, uint16_t value)

diff --git a/src/platform/mega_avr/common/hal/timer/timer8.h b/src/platform/mega_avr/common/hal/timer/timer8.h
@@ -54,6 +54,7 @@ static void timer8_config_ps(const timer_port_t *port, unsigned int ps)
 	}
 
 	MMIO8(port->baddr + TCCRB_8B_OFFSET) = reg;
+	MMIO8(port->baddr + TCNT_8B_OFFSET) = 0;
 }
 
 static void timer8_config_op_mode(const timer_port_t *port, bool en, bool inv)

diff --git a/src/platform/sifive/common_fe310/hal/clint/clint.c b/src/platform/sifive/common_fe310/hal/clint/clint.c
@@ -46,6 +46,7 @@ static status_t clint_setup()
 	port->baddr = dp->baddr;
 	port->stride = dp->stride;
 	port->port_id = clint;
+	MMIO64(port->baddr + MTIME_OFFSET) = 0;
 	return success;
 }