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Arch: MIPSIssues with the MIPS architecture pluginIssues with the MIPS architecture pluginComponent: ArchitectureIssue needs changes to an architecture pluginIssue needs changes to an architecture pluginEffort: MediumIssue should take < 1 monthIssue should take < 1 monthImpact: MediumIssue is impactful with a bad, or no, workaroundIssue is impactful with a bad, or no, workaroundLiftingissues related to LLIL liftingissues related to LLIL lifting
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MIPS5 (and 4?) have optional DSP instructions. As is typical of DSP instruction sets, there's lots of them, most of which are rare outside actual DSP code. However, some compilers appear to frequently generate DSP instructions for normal, pure-integer C code. BN hits these during analysis, believes they're undefined, and terminates the function there.
The culprits here appear to be the "load byte/hword/word indexed" instructions (LBUX, LHX, LWX)- which just load from an address calculated as the sum of two registers (i.e. foo = mem.d[bar+baz];
).
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Arch: MIPSIssues with the MIPS architecture pluginIssues with the MIPS architecture pluginComponent: ArchitectureIssue needs changes to an architecture pluginIssue needs changes to an architecture pluginEffort: MediumIssue should take < 1 monthIssue should take < 1 monthImpact: MediumIssue is impactful with a bad, or no, workaroundIssue is impactful with a bad, or no, workaroundLiftingissues related to LLIL liftingissues related to LLIL lifting