⏰ VLSI Digital Clock With Alarm Functionality

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📖 Overview

The VLSI Digital Clock With Alarm Functionality is a Verilog HDL-based RTL design that implements a real-time digital clock with configurable alarm support, snooze control, PWM-based buzzer generation, and seven-segment display interfacing.

The project demonstrates essential VLSI and FPGA design concepts including hierarchical RTL development, finite state machine (FSM) design, digital counters, alarm scheduling, display multiplexing, and functional verification through simulation.

The architecture follows a modular design methodology, making it scalable, reusable, and suitable for FPGA implementation and academic RTL design projects.

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✨ Features

• Real-Time HH:MM:SS Timekeeping
• 24-Hour Clock Format
• Alarm Scheduling and Activation
• Snooze Functionality
• PWM-Based Buzzer Control
• Seven-Segment Display Interface
• Modular RTL Architecture
• FSM-Based User Control Logic
• Self-Checking Verification Environment
• GTKWave Waveform Analysis
• FPGA-Oriented Design Methodology

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🏗️ System Architecture

The Digital Clock with Alarm Functionality follows a modular RTL architecture consisting of multiple interconnected modules responsible for timekeeping, user interaction, alarm management, display control, and buzzer generation.

Major Modules

Module	Description
UI FSM	Handles user interaction and mode selection
Time Core	Maintains hour, minute, and second counters
Alarm FSM	Performs alarm comparison and activation
Buzzer PWM	Generates PWM output for alarm indication
Seven Segment Driver	Controls multiplexed display output
Debounce Synchronizer	Filters mechanical button noise
Clock Enable Generator	Produces timing pulses

Design Hierarchy

Top Module
├── UI FSM
├── Time Core
├── Alarm FSM
├── Buzzer PWM
├── Seven Segment Driver
├── Debounce Synchronizer
└── Clock Enable Generator

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🔄 System Flow

Operational Flow

1. System Reset
2. Clock Initialization
3. Normal Timekeeping
4. User Configuration Mode
5. Alarm Configuration
6. Time Comparison
7. Alarm Trigger Detection
8. Buzzer Activation
9. Snooze Handling
10. Continuous Operation

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📂 Repository Structure

VLSI-Digital-Clock-With-Alarm-Functionality/
│
├── docs/
│   ├── Architecture.md
│   ├── FPGA_Implementation.md
│   └── Verification.md
│
├── images/
│   ├── project_banner.png
│   └── system_flow.png
│
├── reports/
│   └── Digital_Clock_Project_Report.md
│
├── rtl/
│   ├── alarm_fsm.v
│   ├── buzzer_pwm.v
│   ├── clk_enable.v
│   ├── debounce_sync.v
│   ├── seg_mux.v
│   ├── time_core.v
│   ├── top.v
│   └── ui_fsm.v
│
├── tb/
│   ├── assertions.sv
│   └── tb_top.sv
│
├── waveforms/
│   ├── 01_timekeeping_engine.png
│   ├── 02_seconds_rollover.png
│   ├── 03_minute_rollover.png
│   ├── 04_hour_rollover.png
│   ├── 05_day_rollover.png
│   └── 06_alarm_trigger.png
│
├── README.md
├── LICENSE
└── .gitignore

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🧩 RTL Modules

🔹 UI FSM

• Mode Selection
• Time Configuration
• Alarm Configuration
• Snooze Management

🔹 Time Core

• Seconds Counter
• Minutes Counter
• Hours Counter
• Counter Rollover Logic

🔹 Alarm FSM

• Alarm Time Matching
• Alarm State Management
• Alarm Trigger Generation

🔹 Buzzer PWM

• PWM Signal Generation
• Alarm Sound Control

🔹 Seven Segment Driver

• Display Multiplexing
• Segment Encoding
• Real-Time Display Updates

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🛠️ Tools Used

Tool	Purpose
Verilog HDL	RTL Design
Icarus Verilog	Simulation
GTKWave	Waveform Analysis
VS Code	Development Environment
Git & GitHub	Version Control

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▶️ Simulation Flow

Compile Design

iverilog -g2012 -o sim.out rtl/*.v tb/tb_top.sv

Run Simulation

vvp sim.out

Open Waveforms

gtkwave digital_clock.vcd

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📊 Verification Results

1️⃣ Timekeeping Engine Verification

Objective: Verify normal HH:MM:SS counting operation.

Result: PASS ✅

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2️⃣ Seconds Rollover Verification

Objective: Verify 59 → 00 second rollover behavior.

Result: PASS ✅

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3️⃣ Minute Rollover Verification

Objective: Verify minute counter rollover and carry propagation.

Result: PASS ✅

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4️⃣ Hour Rollover Verification

Objective: Verify correct hour increment operation.

Result: PASS ✅

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5️⃣ Day Rollover Verification

Objective: Verify transition from 23:59:59 to 00:00:00.

Result: PASS ✅

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6️⃣ Alarm Trigger Verification

Objective: Verify alarm activation when current time matches programmed alarm time.

Result: PASS ✅

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📈 Verification Summary

Test Case	Description	Status
TC-01	Timekeeping Engine	✅ PASS
TC-02	Seconds Rollover	✅ PASS
TC-03	Minute Rollover	✅ PASS
TC-04	Hour Rollover	✅ PASS
TC-05	Day Rollover	✅ PASS
TC-06	Alarm Trigger Verification	✅ PASS

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🎯 Key Design Highlights

• Hierarchical RTL Architecture
• FSM-Based Control Logic
• Counter-Based Timekeeping Engine
• Alarm Scheduling and Triggering
• PWM-Based Buzzer Generation
• Seven-Segment Display Multiplexing
• Modular and Reusable RTL Components
• Comprehensive Verification Methodology
• FPGA Deployment Ready

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📚 Documentation

Detailed project documentation is available in:

• 📄 docs/Architecture.md
• 📄 docs/Verification.md
• 📄 docs/FPGA_Implementation.md
• 📄 reports/Digital_Clock_Project_Report.md

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🚀 Future Enhancements

• Multiple Alarm Support
• Stopwatch Mode
• Countdown Timer
• RTC Integration
• UART Configuration Interface
• OLED/LCD Display Support
• Bluetooth Connectivity
• Mobile Application Integration

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👩‍💻 Author

Vaishnava Devi

Connect With Me

🔗 GitHub: https://github.com/VaishnavaDevi-R

🔗 LinkedIn: https://www.linkedin.com/in/vaishnava-devi-141142321/

🔗 Instagram: https://www.instagram.com/_vaishforge_/

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🌟 Support

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📜 License

This project is licensed under the MIT License.