This repository contains the second phase of the Electronics II course project, focusing on the frequency response analysis and small-signal modeling of a MOSFET differential amplifier.
The design follows a modular approach for the analog integrated circuit, ensuring optimal biasing and signal processing performance. The circuit is segmented into the following stages:
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Input Stage (Red): Cascode differential input stage to maximize gain and frequency response.
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Buffer (White): Impedance matching and signal buffering.
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Biasing Sources (Purple): Precision DC current sources for stable operation.
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Current Mirrors (Green): Active loads and biasing for current steering.
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Vbe Multiplier (Blue): Bias voltage generation for class-AB output stages.
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Output Stage (Pink): Power stage designed for high-current driving capability.
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Feedback Network (Orange): Closing the loop for linearity and gain control.
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Magnitude Response: The circuit exhibits a stable mid-band gain as predicted by theoretical small-signal analysis.
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Phase Margin: Phase shift analysis confirms stability and bandwidth limits of the CMOS architecture.
- /Simulations: Contains all LTspice (.asc) files.
- /Report: Contains the final technical report (PDF).
- Topology: CMOS Differential Amplifier.
- Analysis: Small-signal AC analysis, gain-bandwidth product (GBW) calculation, and frequency response verification.
- Simulation Tool: LTspice XVII.
- Design & Theoretical Analysis
- LTspice Simulation
- Documentation
Vahid Hamzeh | Sharif University of Technology