Error in SRAM creation with banks #228
Description
In OpenRAM when creating an SRAM with the following configuration
num_words = 256
words_per_row = 1
tech_name = "sky130"
num_banks = 2
num_rw_ports = 1
num_r_ports = 0
num_w_ports = 0
num_spare_rows = 1
num_spare_cols = 1
process_corners = [ "TT" ]
supply_voltages = [ 3.3 ]
temperatures = [ 25 ]
output_path = "sram_32x32"
output_name = "sram_32x32"
num_threads = 25
num_sim_threads = 25
verbose=10
drc_name = "magic"
lvs_name = "netgen"
pex_name = "magic"
It throws error:
ERROR: file simulation.py: line 605: Could not find bl net in timing paths.
Traceback (most recent call last):
File "sram_compiler.py", line 76, in <module>
s.save()
File "/home/iiitb/tools/OpenRAM/compiler/sram.py", line 130, in save
d.analysis_init(probe_address, probe_data)
File "/home/iiitb/tools/OpenRAM/compiler/characterizer/delay.py", line 1288, in analysis_init
self.set_internal_spice_names()
File "/home/iiitb/tools/OpenRAM/compiler/characterizer/simulation.py", line 520, in set_internal_spice_names
bl_name_port, br_name_port = self.get_bl_name(self.graph.all_paths, port)
File "/home/iiitb/tools/OpenRAM/compiler/characterizer/simulation.py", line 624, in get_bl_name
bl_names.append(self.get_alias_in_path(paths, int_net, cell_mod, exclude_set))
File "/home/iiitb/tools/OpenRAM/compiler/characterizer/simulation.py", line 605, in get_alias_in_path
debug.error("Could not find {} net in timing paths.".format(internal_net), 1)
File "/home/iiitb/tools/OpenRAM/compiler/debug.py", line 48, in error
assert return_value == 0
AssertionError
When the num_banks is set to 1, the SRAM memory is created. Is the memory bank functionality working in OpenRAM